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FQP13N50C 数据表(PDF) 6 Page - Fairchild Semiconductor |
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FQP13N50C 数据表(HTML) 6 Page - Fairchild Semiconductor |
6 / 17 page AN-8027 © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.0 • 8/26/09 6 [STEP-1] Define System Specifications Since the overall system is comprised of two stages (PFC and DC/DC), as shown in Figure 12, the input power and output power of the boost stage are given as: OUT IN P P η = (8) OUT BOUT PWM P P η = (9) where η is the overall efficiency and η PWM is the forward converter efficiency. The nominal output current of boost PFC stage is given as: OUT BOUT PWM BOUT P I V η = (10) Boost PFC Forward DC/DC P IN P BOUT V BOUT I BOUT P OUT V OUT Figure 12. Two Stage Configuration (Design Example) 300 366 0.82 OUT IN P P W η == = 300 349 0.86 OUT BOUT PWM P P W η == = 300 0.86 387 0.9 OUT BOUT PWM BOUT P I A V η ⋅ == = [STEP-2] Frequency Setting The switching frequency is determined by the timing resistor and capacitor (RT and CT) as: 11 40.56 SW TT f R C ≅⋅ ⋅⋅ (11) It is typical to use a 470pF~1nF capacitor for 50~75kHz switching frequency operation since the timing capacitor value determines the maximum duty cycle of PFC gate drive signal as: . . 11 360 MIN OFF MAX PFC T SW SW T D Cf T =− =− ⋅ ⋅ (12) (Design Example) Since the switching frequency is 65kHz, CT is selected as 1nF. Then the maximum duty cycle of PFC gate drive signal is obtained as: . 1 360 0.98 MAX PFC T SW DC f = −⋅ ⋅ = The timing resistor is determined as: 11 6.9 40.56 T SW T R k fC = ⋅= Ω [STEP-3] Line Sensing Circuit Design FAN480X senses the RMS value and instantaneous value of line voltage using the VRMS and IAC pins, respectively, as shown in Figure 13. The RMS value of the line voltage is obtained by an averaging circuit using low pass filter with two poles. Meanwhile, the instantaneous line voltage information is obtained by sensing the current flowing into IAC pin through RIAC. IA C VRMS R RMS1 R RMS2 R RMS3 C RMS1 C RMS2 R IAC I AC V IN I L 120/100Hz f p1 f p2 RMS IN V V Figure 13. Line Sensing Circuits RMS sensing circuit should be designed considering the nominal operation range of line voltage and brownout protection trip point as: 3 . 12 3 2 2 RMS RMS UVL LINE BO RMS RMS RMS R VV RR R π − = ⋅ ++ (13) 3 . 12 3 2 RMS RMS UVH LINE MIN RMS RMS RMS R VV RR R − < ++ (14) where VRMS-UVL and VRMS-UVH are the brown OUT/IN thresholds of VRMS. It is typical to set RRMS2 as 10% of RRMS1. The poles of the low pass filter are given as: 1 12 1 2 P RMS RMS f CR π ≅ ⋅⋅ (15) 2 23 1 2 P RMS RMS f CR π ≅ ⋅⋅ (16) |
类似零件编号 - FQP13N50C |
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类似说明 - FQP13N50C |
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