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FAN3213T 数据表(PDF) 8 Page - Fairchild Semiconductor |
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FAN3213T 数据表(HTML) 8 Page - Fairchild Semiconductor |
8 / 12 page AN-6069 APPLICATION NOTE © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.3 • 1/6/10 8 Figure 17. Compound Driver Output Stage For compound drivers, the output current is often specified with the output voltage at a specified voltage, such as VDD/2, to highlight the current that is available during the Miller plateau region of the VGS waveform. In tests performed using the methods described in section “Evaluating Drivers on the Bench” below, the peak output current is generally higher than the current specified at VDD/2. Figure 18 shows the sink current capability of a 4A compound driver (FAN3224C) to be 4.76A, while the output is at 6.1V after reaching a peak just under 6A. A compound driver rated at 4A might deliver a higher peak current than a comparably rated PMOS/NMOS driver. This type of information is practically impossible to obtain from the driver datasheets, so specific test methods are required. IOUT at 2A/div VOUT at 5V/div INPUT at 10V/div Time = 200ns/div Figure 18. Compound Driver Current Sink Waveform Evaluating Drivers on the Bench Real-world driver comparisons are difficult to perform in the lab because the fast signal ramp rates cause complex interactions between the inductive and capacitive circuit components. These fast edge rates can introduce overshoots and undershoots of several volts. Some examples to help quantify this effect in power circuits can be found in reference [5]. Although the parasitic inductance varies according to specific circuit layout and ground structure, reference [6] gives an approximate value of 10nH/inch (4nH/cm) for microstrip on FR-4 with the trace exposed to air on one side. This provides an estimate that can be used with the circuit capacitance to calculate a damping resistor when needed. It is difficult to compare competing devices using only datasheets, which offer information produced using different test conditions. Competing technologies used in integrated circuit solutions further complicate device comparison. In the following paragraphs, several circuits that can be used to test and compare drivers on the bench are presented. Figure 19 shows a circuit that can be used to test the pulsed current source capability of a driver by clamping VOUT to a level equal to VDSCH + VDZEN when the output is high. To minimize power dissipation, the input is driven with a 200ns positive-going pulse (for non-inverting driver) with a 2% duty cycle. In this circuit, the positive-going voltage across RCS is used to monitor the current sourced out of the driver. To change the value of the output clamping voltage, the voltage rating of DZEN must be changed. VDD RCS VPULSE DZEN DSCH VCS + - CBYP VOUT Figure 19. Current Source Test Circuit with Clamped VOUT Figure 20 shows a circuit used to test the pulsed current sink capability of a driver with the output voltage clamped at a level VADJ-VDSCH. Here, the input is driven with a 200ns negative-going pulse (for a non-inverting driver) with a 2% duty cycle. In this circuit, the negative-going voltage across RCS is used to monitor the current that the driver is sinking. Figure 20. Current Sink Test Circuit with Clamped VOUT |
类似零件编号 - FAN3213T |
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类似说明 - FAN3213T |
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