LC07424LP

No.A1619-7/32

Oparating condistion

Absolute Maximum Ratings at Ta=25±2

°C, VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig= 0V

Parameter

Symbol

min

max

unit

Supply voltage (4.8V sistem) (*1) (*2)

VDD48

-0.3

+7.0

V

Supply voltage (2.8V sistem) (*1) (*3)

VDD28

-0.3

+4.0

V

Supply voltage (1.8V sistem) (*1) (*4)

VDD18

-0.3

+4.0

V

Analog input voltage (*5)

VINana

-0.3

VDD28 + 0.3

V

Digital input voltage (*6)

VINdig

-0.3

VDD18 + 0.3

V

Allowable power dissipation (*7)

Pd

400

mW

Operating ambient temperature

Topr

-10

+80

°C

Storage ambient temperature

Tstg

-55

+125

°C

(*1) The supply voltage including rise/fall must maintain the following relationship:

VDD48 ≥ VDD28 ≥ VDD18

(*2) 4.8V system power pin: VDDh, VDDvh

(*3) 2.8V system power pin: VDDana, VDDsp, VDDv

(*4) 1.8V system power pin: VDDio, VDDdig, VDDio ≥ VDDdig

(*5) Applicable pins: YIN, CIN, LIN_L LIN_R

(*6) Applicable pins: MCLK, TESTin, RESET_X, CS_X, SCLK, SDin, BCLK, LRCLK (for the input mode), G_PORT2 / 1 / 0 (for the input mode; the output

mode only in case of normal operation)

(*7) Ta ≤ 80

°C, our standard substrate (size: 40 mm x 50 mm x 0.8 mm. In case of mounting of four-layer glass epoxy (2S2P) )

Recommended Operating Range at VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig=0V

Parameter

Symbol

Conditions

min

typ

max

unit

VDDio

VDDio pin (*1)

1.71

1.80

3.6

V

VDDdig

VDDdig pin (*1)

1.71

1.80

VDDio

V

VDDana

VDDana, VDDv, VDDsp pin (*1)

2.6

2.8

3.6

V

Supply voltage

VDDh

VDDh, VDDvh pin (*1)

4.5

4.8

5.5

V

Inpupt high level voltage

VIH

(*2)

(0.8)VDDio

VDDio

V

Input low level voltage

VIL

(*2)

VSS

(0.2)VDDio

V

Input clock frequency

fMCLK

(*3)

8.192

12.288

MHz

fs=32kHz (*3)

30

50

70

%

Input clock duty

DutyMCLK

fs=48kHz, 44.1kHz (*3)

45

50

55

%

Analog line input dynamic range

L_IN

LIN_L, LIN_R pin (*4)

(0.9)VDDana

Vp-p

(*1) VDDh=VDDvh, VDDana=VDDsp=VDDv ≥ VDDio ≥ VDDdig

(*2) Applicable pins: MCLK, TESTin, RESET_X, CS_X, SCLK, SDin, BCLK (for the input mode LRCLK (for the input mode), G_PORT2 / 1 / 0 (for the input

mode; the output mode only in case of normal operation)

(*3) MCLK pin 8.192MHz => 32kHz x 256 12.288MHz => 48kHz x 256

(*4) Specifications of the input selector circuit. The PGA output is not to exceed the full scale of ADC input.

Electrical Characteristics at Ta=25±2

°C, VDDh=VDDvh= 4.5 to 5.5V, VDDana=VDDsp=VDDv=2.6 to 3.6V

VDDio=VDDdig=1.71 to 3.6V, VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig=0V

Parameter

Symbol

Conditions

min

typ

max

unit

Input high level current

IIH

VI=VDDio (*1)

+1

μA

Inputp low level current

IIL

VI=VSS (*1)

-1

μA

Output high level voltage

VOH1

IOH=-1mA (*2)

(0.8)VDDio

V

Output low level voltage

VOL1

IOL= 1mA (*2)

(0.2)VDDio

V

Input leak current

ILK

VI=VDDio or VSS (*3)

-10

+10

μA

(*1) Applicable pins: MCLK, TESTin, RESET_X, CS_X, SCLK, SDin,

(*2) Applicable pins: ADC_DOUT

BCLK, LRCLK (Output mode)

G_PORT2 / 1 / 0 (For the output mode. Output mode only in case of normal operation.)

(*3) Applicable pins: BCLK, LRCLK (Output mode)

G_PORT2 / 1 / 0 (For the input mode. Output mode only in case of normal operation.)