Table 1 Input Data Functions

No. 4922-9/21

LC72146, 72146M

No.

Name

Function

Related bits

Programmable divider ratio

P15 is the MSB. The divider ratio, frequency range and lsb are determined by the setting of the DVS and

SNS flags as shown in Table 2 and Table 3. P0 to P3 are ignored if P4 is the LSB.

Table 2 Divider ratio settings

Note:

× = don’t care

Table 3 Frequency range settings

Note:

× = don’t care

Sub-charge pump control

Bits PDC0 and PDC1 control the charge pump state as shown in Table 4. The sub-charge pump is

connected to the gate of the low-pass filter transistor. This can be used in conjunction with PD0 and PD1

(main charge pump) to build a fast locking PLL.

Table 4 Charge pump state selection

Note:

× = don’t care

* See the “Charge Pump” on page 16 for details.

Reference frequency select

Bits R0 to R3 disable the PLL or select the reference frequency as shown in Table 5.

Table 5 Reference frequency selection

When the PLL is disabled, the programmable divider is stopped, AMIN and FMIN are pulled to ground,

and the charge-pump outputs become high impedance.

DVS

SNS

LSB

Divider ratio (N)

1

×

P0

272 to 65535

0

1

P0

272 to 65535

0

0

P4

4 to 4095

DVS

SNS

Input port

Input frequency range (MHz)

1

×

FMIN

10 to 160

0

1

AMIN

2 to 40

0

0

AMIN

0.5 to 10

PDC0

PDC1

Charge pump state

0

×

High impedance

1

1

Operating (operates continuously)

1

0

Operating (when PLL is unlocked)

Reference frequency (kHz)

0

0

0

0

100

0

0

0

1

50

0

0

1

0

25

0

0

1

1

25

0

1

0

0

12.5

0

1

0

1

6.25

0

1

1

0

3.125

0

1

1

1

3.125

1

0

0

0

10

1

0

0

1

9

1

0

1

0

5

1

0

1

1

1

1

1

0

0

3

1

1

0

1

30

1

1

1

0

PLL inhibited and crystal oscillator stopped

1

1

1

1

PLL inhibited

P0 to P15,

DVS, SNS

(1)

PDC0,

PDC1

(2)

R0 to R3

(3)

UL0, UL1, DLC

Continued on next page.