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STCD1030 数据表(PDF) 11 Page - STMicroelectronics |
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STCD1030 数据表(HTML) 11 Page - STMicroelectronics |
11 / 40 page STCD1020, STCD1030, STCD1040 Device operation Doc ID 13823 Rev 6 11/40 3 Device operation The STCD1020, STCD1030 and STCD1040 are 2, 3 or 4 buffered unity gain clock distribution circuits. They accept the clock input from an external clock source and send 2, 3 or 4 buffered outputs to different devices. Each clock output of the STCD1020, STCD1030 and STCD1040 can be enabled for the device connected to it. If the device connected is in standby and does not require a clock, the buffer can be disabled to save power consumption. If all the devices connected are in standby, the STCD1020, STCD1030 and STCD1040 will also be put into standby mode for further power consumption saving. The enable signals and output clock signals truth table are given in Table 3. The input DC cut capacitor is embedded in STCD1020, STCD1030 and STCD1040. A capacitor outside is needed for each of the clock outputs. The STCD1020, STCD1030 and STCD1040 are internally biased at 1/2 VCC DC voltage level at the outputs. Note: "0" means logic low and "1" means logic high. When NO CLOCK outputs, the CLKx pins stay at high impedance. Table 3. Truth table for enable signals (EN 1-4) and output clocks (CLK1-4) EN1 EN2 EN3 EN4 CLK1 CLK2 CLK3 CLK4 0 0 0 0 NO CLOCK NO CLOCK NO CLOCK NO CLOCK 1 0 0 0 CLOCK NO CLOCK NO CLOCK NO CLOCK 1 1 0 0 CLOCK CLOCK NO CLOCK NO CLOCK ... ... ... ... ... ... ... ... 1 1 1 1 CLOCK CLOCK CLOCK CLOCK |
类似零件编号 - STCD1030 |
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类似说明 - STCD1030 |
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