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TDA8034AT 数据表(PDF) 6 Page - NXP Semiconductors |
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TDA8034AT 数据表(HTML) 6 Page - NXP Semiconductors |
6 / 29 page TDA8034T_TDA8034AT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2.0. — 12 November 2010 6 of 29 NXP Semiconductors TDA8034T; TDA8034AT Smart card interface The voltage supervisor monitors the voltage of the VDDP and VDD supplies providing both Power-On Reset (POR) and supply drop-out detection during a card session. The supervisor threshold voltages for VDDP and VDD are set internally. As long as VDD is less than Vth + Vhys, the IC remains inactive irrespective of the command line levels. After VDD has reached a level higher than Vth + Vhys, the IC remains inactive for the duration of tw. The output of the supervisor is sent to a digital controller in order to reset the TDA8034T/TDA8034AT. This defined reset pulse of approximately 8 ms, i.e. (tw = 1024 × 1 ∨ fosc(int)low), is used internally to maintain the IC in the Shutdown mode during the supply voltage power on; see Figure 4. A deactivation sequence is performed when either VDD or VDDP falls below Vth. Remark: fosc(int)low is the low frequency (or inactive) mode of the defined fosc(int) parameter. 8.3 Clock circuits The clock signal from pin CLK to the card is either supplied by an external clock signal connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and XTAL2. The TDA8034T/TDA8034AT automatically detects if an external clock is connected to XTAL1, eliminating the need for a separate pin to select the clock source. Automatic clock source detection is performed on each activation command (falling edge of the signal on pin CMDVCCN). The presence of an external clock on pin XTAL1 is checked during a time window defined by the internal oscillator. If a clock is detected, the internal crystal oscillator is stopped. If a clock is not detected, the internal crystal oscillator is started. When an external clock is used, it is mandatory that the clock is applied to pin XTAL1 before the falling edge of the signal on pin CMDVCCN. Fig 4. Voltage supervisor waveforms 001aak993 tw tw power on supply dropout power off Vth + Vhys Vth VDD ALARMN (internal signal) |
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