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74AHC126PW 数据表(PDF) 1 Page - NXP Semiconductors |
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74AHC126PW 数据表(HTML) 1 Page - NXP Semiconductors |
1 / 15 page 1. General description The 74AHC126; 74AHCT126 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC126; 74AHCT126 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state. The 74AHC126; 74AHCT126 is identical to the 74AHC125; 74AHCT125 but has active HIGH output enable inputs. 2. Features I Balanced propagation delays I All inputs have Schmitt-trigger action I Inputs accept voltages higher than VCC I Input levels: N For 74AHC126: CMOS level N For 74AHCT126: TTL level I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74AHC126; 74AHCT126 Quad buffer/line driver; 3-state Rev. 04 — 12 August 2009 Product data sheet |
类似零件编号 - 74AHC126PW |
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类似说明 - 74AHC126PW |
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