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74AHC74PW 数据表(PDF) 5 Page - NXP Semiconductors |
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74AHC74PW 数据表(HTML) 5 Page - NXP Semiconductors |
5 / 18 page 74AHC_AHCT74_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 9 June 2008 5 of 18 NXP Semiconductors 74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; ↑ = LOW to HIGH transition; Qn+1 = state after the next LOW to HIGH CP transition; X = don’t care. 7. Limiting values [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 packages: above 70 °C the value of P tot derates linearly at 8 mW/K. For TSSOP14 packages: above 60 °C the value of P tot derates linearly at 5.5 mW/K. For DHVQFN14 packages: above 60 °C the value of P tot derates linearly at 4.5 mW/K. Table 3. Function table[1] Control Input Output nSD nRD nCP nD nQ nQ nQn+1 nQn+1 LH X X H L LH HL X X L H HL LLX X H H - - HH ↑ L- - L H HH ↑ H- - H L Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK input clamping current VI < −0.5 V [1] −20 - mA IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] −20 +20 mA IO output current VO = −0.5V to (VCC + 0.5 V) −25 +25 mA ICC supply current - +75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +125 °C [2] - 500 mW |
类似零件编号 - 74AHC74PW |
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类似说明 - 74AHC74PW |
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