ISL22316UFRT10Z datasheet(5/15 Pages) INTERSIL

部件名	ISL22316UFRT10Z

功能描述	Single Digitally Controlled Potentiometer XDCP

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制造商	INTERSIL [Intersil Corporation]

网页	http://www.intersil.com/cda/home

标志

5 / 15 page

5

FN6186.2

September 1, 2009

EEPROM SPECIFICATION

EEPROM Endurance

1,000,000

Cycles

EEPROM Retention

Temperature T

≤ +55°C

50

Years

tWC

(Note 17)

Non-volatile Write Cycle Time

12

20

ms

SERIAL INTERFACE SPECIFICATIONS

VIL

A1, A0, SHDN, SDA, and SCL Input Buffer

LOW Voltage

-0.3

0.3*VCC

V

VIH

A1, A0, SHDN, SDA, and SCL Input Buffer

HIGH Voltage

0.7*VCC

VCC + 0.3

V

Hysteresis SDA and SCL Input Buffer Hysteresis

0.05*VCC

V

VOL

SDA Output Buffer LOW Voltage, Sinking

4mA

00.4

V

Cpin

(Note 18)

A1, A0, SHDN, SDA, and SCL Pin

Capacitance

10

pF

fSCL

SCL Frequency

400

kHz

tsp

Pulse Width Suppression Time at SDA and

SCL Inputs

Any pulse narrower than the max spec is

suppressed

50

ns

tAA

SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VCC, until

SDA exits the 30% to 70% of VCC window

900

ns

tBUF

Time the Bus Must be Free Before the Start

of a New Transmission

SDA crossing 70% of VCC during a STOP

condition, to SDA crossing 70% of VCC

during the following START condition

1300

ns

tLOW

Clock LOW Time

Measured at the 30% of VCC crossing

1300

ns

tHIGH

Clock HIGH Time

Measured at the 70% of VCC crossing

600

ns

tSU:STA

START Condition Setup Time

SCL rising edge to SDA falling edge; both

crossing 70% of VCC

600

ns

tHD:STA

START Condition Hold Time

From SDA falling edge crossing 30% of VCC

to SCL falling edge crossing 70% of VCC

600

ns

tSU:DAT

Input Data Setup Time

From SDA exiting the 30% to 70% of VCC

window, to SCL rising edge crossing 30% of

VCC

100

ns

tHD:DAT

Input Data Hold Time

From SCL rising edge crossing 70% of VCC

to SDA entering the 30% to 70% of VCC

window

0ns

tSU:STO

STOP Condition Setup Time

From SCL rising edge crossing 70% of VCC,

to SDA rising edge crossing 30% of VCC

600

ns

tHD:STO

STOP Condition Hold Time for Read, or

Volatile Only Write

From SDA rising edge to SCL falling edge;

both crossing 70% of VCC

1300

ns

tDH

Output Data Hold Time

From SCL falling edge crossing 30% of

VCC, until SDA enters the 30% to 70% of

VCC window

0ns

tR

SDA and SCL Rise Time

From 30% to 70% of VCC

20 +

0.1*Cb

250

ns

tF

SDA and SCL Fall Time

From 70% to 30% of VCC

20 +

0.1*Cb

250

ns

Cb

Capacitive Loading of SDA or SCL

Total on-chip and off-chip

10

400

pF

Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 19)

TYP

(Note 5)

MAX

(Note 19)

UNIT

ISL22316

类似零件编号 - ISL22316UFRT10Z

制造商	部件名	数据表	功能描述
Intersil Corporation	ISL22316UFRT10Z	605Kb / 16P	Low Noise, Low Power I2C??Bus,128 Taps August 14, 2015
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