ISLA112P25MREP

4

FN7646.0

June 25, 2010

54

D8P

[D8]

LVDS Bit 8 Output True

[LVCMOS Bit 8]

DDR Logical Bits 9,8 (LVDS or CMOS)

57

D9N

[NC]

LVDS Bit 9 Output Complement

[NC in LVCMOS]

NC in DDR

58

D9P

[D9]

LVDS Bit 9 Output True

[LVCMOS Bit 9]

NC in DDR

59

D10N

[NC]

LVDS Bit 10 Output Complement

[NC in LVCMOS]

DDR Logical Bits 11,10 (LVDS)

60

D10P

[D10]

LVDS Bit 10 Output True

[LVCMOS Bit 10]

DDR Logical Bits 11,10 (LVDS or CMOS)

61

D11N

[NC]

LVDS Bit 11 Output Complement

[NC in LVCMOS]

NC in DDR

62

D11P

[D11]

LVDS Bit 11 Output True

[LVCMOS Bit 11]

NC in DDR

63

ORN

[NC]

LVDS Over Range Complement

[NC in LVCMOS]

64

ORP

[OR]

LVDS Over Range True

[LVCMOS Over Range]

66

SDO

SPI Serial Data Output

(4.7kΩ pull-up to OVDD is required)

67

CSB

SPI Chip Select (active low)

68

SCLK

SPI Clock

69

SDIO

SPI Serial Data Input/Output

70

OUTFMT

Tri-Level Output Data Format Control (Two’s

Comp., Gray Code, Offset Binary)

Exposed Paddle

AVSS

Analog Ground

NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection). SDR is the default state at power-up for

the 72 Ld package.

PIN

NUMBER

LVDS [LVCMOS]

NAME

LVDS [LVCMOS] FUNCTION

SDR MODE

DDR MODE

COMMENTS

Ordering Information

PART NUMBER

PART MARKING

SPEED

(MSPS)

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISLA112P25MREP (Note 1)

ISLA112P25 MREP

250

-55 to +125

72 Ld QFN

L72.10x10D

NOTE:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach

materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free

soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.