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AD5755BCPZx 数据表(PDF) 8 Page - Analog Devices |
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AD5755BCPZx 数据表(HTML) 8 Page - Analog Devices |
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8 / 34 page  AD5755/AD5735 Preliminary Technical Data Rev. PrG | Page 8 of 34 TIMING CHARACTERISTICS AVDD = 15V, AVSS = -15V, VBOOSTA,B,C,D = +10.8 V to +33 V, DVDD = AVCC = 2.7 V to 5.5 V, DCDC disabled, AGND = DGND = GNDSWA,B,C,D = 0 V, REFIN= +5, VOUT : RL = 1kΩ, CL = 220pF, IOUT : RL = 300Ω, all specifications TMIN to TMAX unless otherwise noted. Table 4. Parameter1, 2,3 Limit at TMIN, TMAX Unit Description t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 13 ns min 24/32nd SCLK falling edge to SYNC rising edge t6 198 ns min SYNC high time t7 5 ns min Data setup time t8 5 ns min Data hold time t9 20 µs min SYNC rising edge to LDAC falling edge (all DACs updated or any channel has digital slew rate control enabled) 5 µs min SYNC rising edge to LDAC falling edge (single DAC updated) t10 10 ns min LDAC pulse width low t11 500 ns max LDAC falling edge to DAC output response time t12 See AC Performance Characteristics µs max DAC output settling time t13 10 ns min CLEAR high time t14 TBD µs max CLEAR activation time t15 25 ns max SCLK rising edge to SDO valid (CL SDO = 35 pF) t16 20 µs min SYNC rising edge to DAC output response time (LDAC = 0) (all DACs updated) 5 µs min SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated) t17 500 ns min LDAC falling edge to SYNC rising edge t18 700 ns min RESET pulse width t19 20 µs min SYNC high to next SYNC low (Ramp enabled) 5 µs min SYNC high to next SYNC low (Ramp disabled) 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 2 , Figure 3 , Figure 4 and Figure 5 |
类似零件编号 - AD5755BCPZx |
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类似说明 - AD5755BCPZx |
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