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AD5445YCP 数据表(PDF) 5 Page - Analog Devices |
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AD5445YCP 数据表(HTML) 5 Page - Analog Devices |
5 / 32 page AD5424/AD5433/AD5445 Rev. B | Page 5 of 32 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: −40°C to +125°C ; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 VDD = 2.5 V to 5.5 V VDD = 4.5 V to 5.5 V Unit Conditions/Comments t1 0 0 ns min R/W to CS setup time t2 0 0 ns min R/W to CS hold time t3 10 10 ns min CS low time (write cycle) t4 6 6 ns min Data setup time t5 0 0 ns min Data hold time t6 5 5 ns min R/W high to CS low t7 9 7 ns min CS min high time t8 20 10 ns typ Data access time 40 20 ns max t9 5 5 ns typ Bus relinquish time 10 10 ns max 1 Guaranteed by design, not subject to production test. CS DATA R/W t1 t2 t6 t7 t8 t2 t9 t3 t4 t5 DATA VALID DATA VALID Figure 2. Timing Diagram |
类似零件编号 - AD5445YCP |
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类似说明 - AD5445YCP |
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