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CDCE906PWRG4 数据表(PDF) 11 Page - Texas Instruments

部件名 CDCE906PWRG4
功能描述  PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CDCE906PWRG4 数据表(HTML) 11 Page - Texas Instruments

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APPLICATION INFORMATION
SMBus Data Interface
Data Protocol
Slave Receiver Address (7 bits)
CDCE906
SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. It follows
the SMBus specification Version 2.0, which is based upon the principals of operation of I2C. More details of the
SMBus specification can be found at http://www.smbus.org.
Through the SMBus, various device functions, such as individual clock output buffers, can be individually
enabled or disabled. The registers associated with the SMBus data interface initialize to their default setting upon
power-up, and therefore using this interface is optional. The clock device register changes are normally made
upon system initialization, if any are required.
The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operations from the
controller.
For Block Write/Read operations, the bytes must be accessed in sequential order from lowest to highest byte
(most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and
Byte Read operations, the system controller can access individually addressed bytes.
Once a byte has been sent, it will be written into the internal register and effective immediately. With the rising
edge of the ACK bit, this applies to each transferred byte, independent of whether this is a Byte Write or a Block
Write sequence.
If the EEPROM write cycle is initiated, the data of the internal SMBus register is written into the EEPROM.
During EEPROM write, no data is allowed to be sent to the device via the SMBus until the programming
sequence is completed. Data, however, can be readout during the programming sequence (byte read or block
read). The programming status can be monitored by EEPIP, byte 24 bit 7.
The offset of the indexed byte is encoded in the command code, as described in Table 1.
The Block Write and Block Read protocol is outlined in Figure 9 and Figure 10, while Figure 7 and Figure 8
outlines the corresponding Byte Write and Byte Read protocol.
A6
A5
A4
A3
A2
A1*
A0*
R/W
1
1
0
1
0
0
1
0
* Address bits A0 and A1 are programmable by the Configuration Inputs S0 and S1 (Byte 10 Bit [1:0] and Bit [3:2]. This allows addressing up
to four devices connected to the same SMBus.
Table 1. Command Code Definition
Bit
Description
0 = Block Read or Block Write operation
7
1 = Byte Read or Byte Write operation
(6:0)
Byte Offset for Read and Write operation.
Copyright © 2005–2007, Texas Instruments Incorporated
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