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CDCE906PWR 数据表(PDF) 6 Page - Texas Instruments

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部件名 CDCE906PWR
功能描述  PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
Download  42 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CDCE906PWR 数据表(HTML) 6 Page - Texas Instruments

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DEVICE CHARACTERISTICS
CDCE906
SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007
TIMING REQUIREMENTS (continued)
over recommended ranges of supply voltage, load, and operating-free air temperature
MIN
NOM
MAX
UNIT
tsu(STOP)
STOP setup time
4
µs
tBUS
Bus free time
4.7
µs
tPOR
Time in which the device must be operational after power-on reset
500
ms
over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
OVERALL PARAMETER
All PLLs on, all outputs on,
ICC
Supply current (2)
fout = 80 MHz, fCLK_IN = 27 MHz,
90
115
mA
fvco = 160 MHz
Power down current. Every circuit
ICCPD
fIN = 0 MHz, VCC = 3.6 V
50
µA
powered down except SMBus
Supply voltage Vcc threshold for
VPUC
2.1
V
power up control circuit
All PLLs
80
200
Normal
VCO frequency of internal PLL (any
speed-mode(3)
fVCO
PLL2 with SSC
80
167
MHz
of three PLLs)
High-speed mode(3)
180
300
fOUT
LVCMOS output frequency range(4)
VCC = 2.5 V or 3.3 V
167
MHz
LVCMOS PARAMETER
VIK
LVCMOS input voltage
VCC = 3 V, II = –18 mA
–1.2
V
LVCMOS input current (CLK_IN0 /
II
VI = 0 V or VCC, VCC = 3.6 V
±5
µA
CLK_IN1)
IIH
LVCMOS input current (For S1/S0)
VI = VCC, VCC = 3.6 V
5
µA
IIL
LVCMOS input current (For S1/S0)
VI = 0 V, VCC = 3.6 V
-35
-10
µA
Input capacitance at CLK_IN0 and
VI = 0 V or VCC
CI
3
pF
CLK_IN1
LVCMOS PARAMETER FOR Vccout = 3.3-V Mode
Vccout = 3 V, IOH = –0.1 mA
2.9
VOH
LVCMOS high-level output voltage
Vccout = 3 V, IOH = –4 mA
2.4
V
Vccout = 3 V, IOH = –6 mA
2.1
Vccout = 3 V, IOL = 0.1 mA
0.1
VOL
LVCMOS low-level output voltage
Vccout = 3 V, IOL = 4 mA
0.5
V
Vccout = 3 V, IOL = 6 mA
0.85
All PLL bypass
9
tPLH,
Propagation delay
ns
tPHL
VCO bypass
11
Rise and fall time for output slew
tr0/tf0
Vccout = 3.3 V (20%–80%)
1.7
3.3
4.8
ns
rate 0
Rise and fall time for output slew
tr1/tf1
Vccout = 3.3 V (20%–80%)
1.5
2.5
3.2
ns
rate 1
Rise and fall time for output slew
tr2/tf2
Vccout = 3.3 V (20%–80%)
1.2
1.6
2.1
ns
rate 2
Rise and fall time for output slew
tr3/tf3
Vccout = 3.3 V (20%–80%)
0.4
0.6
1
ns
rate 3 (Default Configuration)
(1)
All typical values are at respective nominal VCC.
(2)
For calculating total supply current, add the current from Figure 2, Figure 3, and Figure 4. Using high-speed mode of the VCO reduces
the current consumption significantly. See Figure 3
(3)
Normal-speed mode or high-speed mode must be selected by the VCO frequency selection bit in Byte 6, Bit [7:5]. The min fVCO can be
lower but impacts jitter-performance.
(4)
The maximum output frequency may be exceeded, but specifications under the Recommended Operating Condition may change and
are no longer assured. Do not exceed the maximum power dissipation of the 20-pin TSSOP package (600 mW at no air flow).
6
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Copyright © 2005–2007, Texas Instruments Incorporated
Product Folder Link(s): CDCE906


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