数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CDCE706PWG4 数据表(PDF) 6 Page - Texas Instruments

Click here to check the latest version.
部件名 CDCE706PWG4
功能描述  PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER
Download  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CDCE706PWG4 数据表(HTML) 6 Page - Texas Instruments

Back Button CDCE706PWG4 Datasheet HTML 2Page - Texas Instruments CDCE706PWG4 Datasheet HTML 3Page - Texas Instruments CDCE706PWG4 Datasheet HTML 4Page - Texas Instruments CDCE706PWG4 Datasheet HTML 5Page - Texas Instruments CDCE706PWG4 Datasheet HTML 6Page - Texas Instruments CDCE706PWG4 Datasheet HTML 7Page - Texas Instruments CDCE706PWG4 Datasheet HTML 8Page - Texas Instruments CDCE706PWG4 Datasheet HTML 9Page - Texas Instruments CDCE706PWG4 Datasheet HTML 10Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 40 page
background image
RECOMMENDED CRYSTAL SPECIFICATIONS
EEPROM SPECIFICATION
TIMING REQUIREMENTS
DEVICE CHARACTERISTICS
CDCE706
SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com
MIN
NOM
MAX
UNIT
fXtal
Crystal input frequency range (fundamental mode)
8
27
54
MHz
ESR
Effective series resistance(1)(2)
15
60
CIN
Input capacitance CLK_IN0 and CLK_IN1
3
pF
(1)
For crystal frequencies above 50 MHz, the effective series resistor should not exceed 50
Ω to assure stable start-up condition.
(2)
For maximum power handling (drive level), see Figure 15.
MIN
TYP
MAX
UNIT
EEcyc
Programming cycles of EEPROM
100
1000
Cycles
EEret
Data retention
10
Years
over recommended ranges of supply voltage, load, and operating-free air temperature
MIN
NOM
MAX
UNIT
CLK_IN REQUIREMENTS
PLL mode
1
200
fCLK_IN
CLK_IN clock input frequency (LVCMOS or differential)
MHz
PLL bypass mode
0
200
tr/tf
Rise and fall time, CLK_IN signal (20% to 80%)
4
ns
dutyREF
Duty cycle, CLK_IN at VCC/2
40%
60%
SMBus TIMING REQUIREMENTS (see Figure 11)
fSCLK
SCLK frequency
100
kHz
th(START)
START hold time
4
µs
tw(SCLL)
SCLK low-pulse duration
4.7
µs
tw(SCLH)
SCLK high-pulse duration
4
50
µs
tsu(START)
START setup time
0.6
µs
th(SDATA)
SDATA hold time
0.3
µs
tsu(SDATA)
SDATA setup time
0.25
µs
tr(SDATA)/
SCLK/SDATA input rise time
1000
ns
tr(SM)
tf(SDATA)/
SCLK/SDATA input fall time
300
ns
tf(SM)
tsu(STOP)
STOP setup time
4
µs
t(BUS)
Bus free time
4.7
µs
t(POR)
Time in which the device must be operational after power-on reset
500
ms
over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
OVERALL PARAMETER
All PLLs on, all outputs on,
ICC
Supply current(2)
fOUT = 80 MHz, fCLK_IN = 27 MHz,
90
115
mA
fVCO = 160 MHz
Every circuit powered down except SMBus,
ICCPD
Power-down current
50
µA
fIN = 0 MHz, VCC = 3.6 V
Supply voltage VCC threshold for power-up
VPUC
2.1
V
control circuit
(1)
All typical values are at nominal VCC.
(2)
For calculating total supply current, add the current from Figure 2, Figure 3, and Figure 4. Using the high-speed mode of the VCO
reduces the current consumption. See Figure 3.
6
Submit Documentation Feedback
Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): CDCE706


类似零件编号 - CDCE706PWG4

制造商部件名数据表功能描述
logo
Texas Instruments
CDCE706 TI-CDCE706 Datasheet
1Mb / 32P
[Old version datasheet]   PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
More results

类似说明 - CDCE706PWG4

制造商部件名数据表功能描述
logo
Texas Instruments
CDC706 TI-CDC706 Datasheet
1Mb / 41P
[Old version datasheet]   PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDCE906 TI-CDCE906 Datasheet
1Mb / 33P
[Old version datasheet]   PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDCE706 TI-CDCE706 Datasheet
1Mb / 32P
[Old version datasheet]   PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDC906 TI-CDC906 Datasheet
1Mb / 39P
[Old version datasheet]   PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDCE906 TI-CDCE906_10 Datasheet
1Mb / 42P
[Old version datasheet]   PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
CDCE937-Q1 TI1-CDCE937-Q1_15 Datasheet
902Kb / 30P
[Old version datasheet]   PROGRAMMABLE 3-PLL VCXO CLOCK SYNTHESIZER
logo
ON Semiconductor
NB3N65027 ONSEMI-NB3N65027 Datasheet
176Kb / 7P
   3.3V Programmable 3-PLL Clock Synthesizer
June, 2011 ??Rev. 2
logo
Texas Instruments
CDCEL824 TI1-CDCEL824 Datasheet
1Mb / 33P
[Old version datasheet]   Programmable 2-PLL Clock Synthesizer
CDCE913 TI1-CDCE913_15 Datasheet
1Mb / 35P
[Old version datasheet]   Programmable 1-PLL VCXO Clock Synthesizer
CDCE913-Q1 TI1-CDCE913-Q1 Datasheet
897Kb / 27P
[Old version datasheet]   Programmable 1-PLL VCXO Clock Synthesizer
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com