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CDCE706PWG4 数据表(PDF) 6 Page - Texas Instruments |
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CDCE706PWG4 数据表(HTML) 6 Page - Texas Instruments |
6 / 40 page RECOMMENDED CRYSTAL SPECIFICATIONS EEPROM SPECIFICATION TIMING REQUIREMENTS DEVICE CHARACTERISTICS CDCE706 SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com MIN NOM MAX UNIT fXtal Crystal input frequency range (fundamental mode) 8 27 54 MHz ESR Effective series resistance(1)(2) 15 60 Ω CIN Input capacitance CLK_IN0 and CLK_IN1 3 pF (1) For crystal frequencies above 50 MHz, the effective series resistor should not exceed 50 Ω to assure stable start-up condition. (2) For maximum power handling (drive level), see Figure 15. MIN TYP MAX UNIT EEcyc Programming cycles of EEPROM 100 1000 Cycles EEret Data retention 10 Years over recommended ranges of supply voltage, load, and operating-free air temperature MIN NOM MAX UNIT CLK_IN REQUIREMENTS PLL mode 1 200 fCLK_IN CLK_IN clock input frequency (LVCMOS or differential) MHz PLL bypass mode 0 200 tr/tf Rise and fall time, CLK_IN signal (20% to 80%) 4 ns dutyREF Duty cycle, CLK_IN at VCC/2 40% 60% SMBus TIMING REQUIREMENTS (see Figure 11) fSCLK SCLK frequency 100 kHz th(START) START hold time 4 µs tw(SCLL) SCLK low-pulse duration 4.7 µs tw(SCLH) SCLK high-pulse duration 4 50 µs tsu(START) START setup time 0.6 µs th(SDATA) SDATA hold time 0.3 µs tsu(SDATA) SDATA setup time 0.25 µs tr(SDATA)/ SCLK/SDATA input rise time 1000 ns tr(SM) tf(SDATA)/ SCLK/SDATA input fall time 300 ns tf(SM) tsu(STOP) STOP setup time 4 µs t(BUS) Bus free time 4.7 µs t(POR) Time in which the device must be operational after power-on reset 500 ms over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1 PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT OVERALL PARAMETER All PLLs on, all outputs on, ICC Supply current(2) fOUT = 80 MHz, fCLK_IN = 27 MHz, 90 115 mA fVCO = 160 MHz Every circuit powered down except SMBus, ICCPD Power-down current 50 µA fIN = 0 MHz, VCC = 3.6 V Supply voltage VCC threshold for power-up VPUC 2.1 V control circuit (1) All typical values are at nominal VCC. (2) For calculating total supply current, add the current from Figure 2, Figure 3, and Figure 4. Using the high-speed mode of the VCO reduces the current consumption. See Figure 3. 6 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): CDCE706 |
类似零件编号 - CDCE706PWG4 |
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类似说明 - CDCE706PWG4 |
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