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TPA3111D1PWPR 数据表(PDF) 4 Page - Texas Instruments |
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TPA3111D1PWPR 数据表(HTML) 4 Page - Texas Instruments |
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4 / 28 page  1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 SD FAULT GND GND GAIN0 GAIN1 AVCC AGND GVDD PLIMIT PVCC PVCC BSN OUTN PGND OUTN BSN BSP OUTP PGND PWP (TSSOP)Package (TopView) INN INP NC 11 12 13 14 18 17 16 15 OUTP BSP PVCC PVCC AVCC TPA3111D1 SLOS618A – AUGUST 2009 – REVISED JULY 2010 www.ti.com AC CHARACTERISTICS TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 200 mVPP ripple from 20 Hz–1 kHz, KSVR Supply ripple rejection –70 dB Gain = 20 dB, Inputs ac-coupled to AGND PO Continuous output power THD+N ≤ 10%, f = 1 kHz , RL = 8Ω 10 W PO Continuous output power THD+N ≤ 0.1%, f = 1 kHz , RL = 4Ω 10 W THD+N Total harmonic distortion + noise RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power) <0.06 % 65 µV Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB –80 dBV Crosstalk Po = 1 W, Gain = 20 dB, f = 1 kHz –70 dB Maximum output at THD+N < 1%, f = 1 kHz, SNR Signal-to-noise ratio 102 dB Gain = 20 dB, A-weighted fOSC Oscillator frequency 250 310 350 kHz Thermal trip point 150 °C Thermal hysteresis 15 °C PIN FUNCTIONS PIN I/O DESCRIPTION NAME Pin # Shutdown logic input for audio amp(LOW = outputs Hi-Z, HIGH = outputs enabled). SD 1 I TTL logic levels with compliance to AVCC. Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT 2 O FAULT pin to SD pin. Otherwise bothe short circuit faults and dc detect faults must be reset by cycling PVCC. GND 3 Connect to local ground GND 4 Connect to local ground GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC. GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC. AVCC 7 P Analog supply. AGND 8 Analog supply ground. Connect to the thermal pad. High-side FET gate drive supply. Nominal voltage is 7V. May also be used as GVDD 9 O supply for PLILMIT divider. Add a 1mF cap to ground at this pin. Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a PLIMIT 10 I 1mF cap to ground at this pin. 4 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPA3111D1 |
类似零件编号 - TPA3111D1PWPR |
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类似说明 - TPA3111D1PWPR |
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