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CDCU2A877 数据表(PDF) 11 Page - Texas Instruments |
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CDCU2A877 数据表(HTML) 11 Page - Texas Instruments |
11 / 16 page www.ti.com t ( ) t ( )dyn t ( )dyn t ( )dyn t ( )dyn t ( ) CDCU2A877 SCAS827A – AUGUST 2006 – REVISED JUNE 2007 Figure 11. Dynamic Phase Offset Figure 12. Time Delay Between OE and Clock Output (Y, Y) A. Place the 2200-pF capacitor close to the PLL. B. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND via (farthest from the PLL). C. Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600Ω at 100 MHz). Figure 13. Recommended AVDD Filtering 11 Submit Documentation Feedback |
类似零件编号 - CDCU2A877_1 |
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类似说明 - CDCU2A877_1 |
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