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SN74AUP1G57DCKRG4 数据表(PDF) 2 Page - Texas Instruments |
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SN74AUP1G57DCKRG4 数据表(HTML) 2 Page - Texas Instruments |
2 / 24 page 3 1 6 In2 In1 In0 4 Y SN74AUP1G57 SCES503I – NOVEMBER 2003 – REVISED MAY 2010 www.ti.com NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION(1) TOP-SIDE TA PACKAGE(2) ORDERABLE PART NUMBER MARKING(3) NanoStar™ – WCSP (DSBGA) Reel of 3000 SN74AUP1G57YFPR _ _ _HH_ 0.23-mm Large Bump – YFP (Pb-free) NanoStar™ – WCSP (DSBGA) Reel of 3000 SN74AUP1G57YZPR _ _ _HH_ 0.23-mm Large Bump – YZP (Pb-free) QFN – DRY Reel of 5000 SN74AUP1G57DRYR HH –40°C to 85°C uQFN – DSF Reel of 5000 SN74AUP1G57DSFR HH SOT (SOT-23) – DBV Reel of 3000 SN74AUP1G57DBVR HA7_ SOT (SC-70) – DCK Reel of 3000 SN74AUP1G57DCKR HH_ SOT (SOT-553) – DRL Reel of 4000 SN74AUP1G57DRLR HH_ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) DBV/DCK/DRL/DRY/DSF: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS OUTPUT Y In2 In1 In0 L L L H L L H L L H L H L H H L H L L L H L H L H H L H H H H H LOGIC DIAGRAM (POSITIVE LOGIC) 2 Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G57 |
类似零件编号 - SN74AUP1G57DCKRG4 |
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类似说明 - SN74AUP1G57DCKRG4 |
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