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SN74AUC2G125DCTR 数据表(PDF) 1 Page - Texas Instruments |
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SN74AUC2G125DCTR 数据表(HTML) 1 Page - Texas Instruments |
1 / 14 page www.ti.com FEATURES 3 2 5 8 1 1OE 1A GND 3 2 4 5 1 V CC V CC V CC 2OE 2OE 2OE 1A GND 1A GND 2A 2Y Seemechanicaldrawingsfordimensions. 2 5 3 4 8 2Y 1Y 1Y 2A 2Y 2A 4 6 7 6 7 8 6 1 7 1OE DCTPACKAGE (TOP VIEW) DCUPACKAGE (TOP VIEW) YZP PACKAGE (BOTTOMVIEW) 1OE 1Y DESCRIPTION/ORDERING INFORMATION SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES532D – DECEMBER 2003 – REVISED AUGUST 2007 • Available in the Texas Instruments • Low Power Consumption, 10 μA at 1.8 V NanoFree™ Package • ±8-mA Output Drive at 1.8 V • Optimized for 1.8-V Operation and Is 3.6-V I/O • Latch-Up Performance Exceeds 100 mA Per Tolerant to Support Mixed-Mode Signal JESD 78, Class II Operation • ESD Protection Exceeds JESD 22 • I off Supports Partial-Power-Down Mode – 2000-V Human-Body Model (A114-A) Operation – 200-V Machine Model (A115-A) • Sub-1-V Operable – 1000-V Charged-Device Model (C101) • Max t pd of 1.8 ns at 1.8 V This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE(1)(2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3) NanoFree™ – WCSP (DSBGA) Reel of 3000 SN74AUC2G125YZPR _ _ _UM_ 0.23-mm Large Bump – YZP (Pb-free) –40 °C to 85°C SSOP – DCT Reel of 3000 SN74AUC2G125DCTR U25_ _ _ VSSOP – DCU Reel of 3000 SN74AUC2G125DCUR U25_ (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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类似说明 - SN74AUC2G125DCTR |
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