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CAT25020VP2I-T3 数据表(PDF) 6 Page - ON Semiconductor

部件名 CAT25020VP2I-T3
功能描述  1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM
Download  15 Pages
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

CAT25020VP2I-T3 数据表(HTML) 6 Page - ON Semiconductor

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CAT25010, CAT25020, CAT25040
http://onsemi.com
6
Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 8−bit address
and data as shown in Figure 5. For the CAT25040, bit 3 of
the write instruction opcode contains A8 address bit.
Internal programming will start after the low to high CS
transition. During an internal write cycle, all commands,
except for RDSR (Read Status Register) will be ignored.
The RDY bit will indicate if the internal write cycle is in
progress (RDY high), or the device is ready to accept
commands (RDY low).
Page Write
After sending the first data byte to the CAT25010/20/40,
the host may continue sending data, up to a total of 16 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following
completion
of
the
write
cycle,
the
CAT25010/20/40 is automatically returned to the write
disable state.
Figure 5. Byte WRITE Timing
SCK
SI
SO
00
00
X*
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
01
23
45
67
8
OPCODE
DATA IN
HIGH IMPEDANCE
BYTE ADDRESS
13 14 15 16 17 18 19 20 21 22 23
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
CS
A0
A7
Figure 6. Page WRITE Timing
SCK
SI
SO
00
00
X* 0
1
0
BYTEADDRESS
Data
Byte 1
01
23
45
67
8
13 14 15 16−23 24−31
Data Byte N
OPCODE
7..1
0
16+(N−1)x8−1..16+(N−1)x8
16+Nx8−1
DATA IN
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
CS
A7
A0
Data
Byte 3
Data
Byte 2


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