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CAT130049JWI-GT3 数据表(PDF) 10 Page - ON Semiconductor |
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CAT130049JWI-GT3 数据表(HTML) 10 Page - ON Semiconductor |
10 / 14 page CAT130xx Doc. No. MD-1121 Rev. B 10 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN (Figure 9). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT130xx can be deter– mined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Figure 9. WRAL Instruction Timing STATUS VERIFY SK CS DI DO STANDBY HIGH-Z 10 1 BUSY READY tSV tHZ tEW tCSMIN DN D0 0 0 |
类似零件编号 - CAT130049JWI-GT3 |
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类似说明 - CAT130049JWI-GT3 |
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