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CAT150021MWI-GT3 数据表(PDF) 9 Page - ON Semiconductor |
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CAT150021MWI-GT3 数据表(HTML) 9 Page - ON Semiconductor |
9 / 15 page CAT15002, CAT15004 © 2008 SCILLC. All rights reserved. 9 Doc. No. MD-1126 Rev. B Characteristics subject to change without notice Byte Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, an 8-bit address and data as shown in Figure 6 (for the CAT15004, bit 3 of the Write instruciton opcode contains address bit A8). Internal programming will start after the low to high CS ¯¯ transition. During an internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored. The RDY ¯¯¯¯ bit will indicate if the internal write cycle is in progress (RDY ¯¯¯¯ high), or the the device is ready to accept commands (RDY ¯¯¯¯ low). Page Write After sending the first data byte to the CAT15002/04, the host may continue sending data, up to a total of 32 bytes, according to timing shown in Figure 7. After each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. If during this process the end of page is exceeded, then loading will “roll over” to the first byte in the page, thus possibly overwriting previoualy loaded data. Following completion of the write cycle, the CAT15002/04 is automatically returned to the write disable state. Figure 6. Byte WRITE Timing Notes: * X = 0 for CAT15002; X = A8 for CAT15004 Dashed Line = mode (1, 1) - - - - - - Figure 7. Page WRITE Timing Notes: * X = 0 for CAT15002; X = A8 for CAT15004 Dashed Line = mode (1, 1) - - - - - - SCK SI SO 00 00 00 1 0 BYTE ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 0 1 2 3 4 5 6 7 8 131415 1617 1819 20 2122 23 CS OPCODE DATA IN HIGH IMPEDANCE X* A7 A0 SCK SI SO 00 00 00 10 BYTE ADDRESS Data Byte 1 01234 5678 13 14 15 16-23 24-31 Data Byte 2 Data Byte 3 Data Byte N CS OPCODE 7..1 0 16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1 DATA IN HIGH IMPEDANCE A7 A0 X* |
类似零件编号 - CAT150021MWI-GT3 |
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类似说明 - CAT150021MWI-GT3 |
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