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CAT24WC66WI-T3C 数据表(PDF) 4 Page - ON Semiconductor

部件名 CAT24WC66WI-T3C
功能描述  64-Kb I2C Serial EEPROM with Partial Array Write Protection
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

CAT24WC66WI-T3C 数据表(HTML) 4 Page - ON Semiconductor

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CAT24WC66
http://onsemi.com
4
Functional Description
The CAT24WC66 supports the I2C Bus data transmission
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
The CAT24WC66 operates as a Slave device. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls which
mode is activated.
Pin Description
SCL: Serial Clock
The serial clock input clocks all data transferred into or out
of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left unconnected (for
hardware compatibility with CAT24WC16). When
hardwired, up to eight CAT24WC66 devices may be
addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the default
values are zeros.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to VCC, the top 1/4
array of memory is write protected. When left floating,
memory is unprotected.
SCL
SDA IN
SDA OUT
Figure 2. Bus Timing
tSU:STA
tF
tSU:STO
tBUF
tR
tDH
tSU:DAT
tLOW
tLOW
tHIGH
tAA
tHD:DAT
tHD:STA
Figure 3. Write Cycle Timing
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
tWR
Figure 4. Start/Stop Timing
START BIT
SDA
STOP BIT
SCL


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