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CAT24AA01WI-T10 数据表(PDF) 7 Page - ON Semiconductor

部件名 CAT24AA01WI-T10
功能描述  1-Kb and 2-Kb I2C CMOS Serial EEPROM
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

CAT24AA01WI-T10 数据表(HTML) 7 Page - ON Semiconductor

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CAT24AA01, CAT24AA02
http://onsemi.com
7
READ OPERATIONS
Immediate Read
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Selective Read
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends an address
byte to the Slave. Rather than completing the Byte Write
sequence by sending data, the Master then creates a START
condition and broadcasts a Slave address with the R/W bit
set to ‘1’. The Slave responds with ACK after every byte sent
by the Master and then sends out data residing at the selected
address. After receiving the data, the Master responds with
NoACK and then terminates the session by creating a STOP
condition on the bus (Figure 11).
Sequential Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory. For the CAT24AA01, the internal address
counter will not wrap around at the end of the 128 byte
memory space.
Figure 10. Immediate Read Sequence and Timing
SCL
SDA
8th Bit
STOP
NO ACK
DATA OUT
89
SLAVE
ADDRESS
S
A
C
K
DATA
BYTE
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
Figure 11. Selective Read Sequence
SLAVE
S
A
C
K
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
S
A
C
K
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
DATA
BYTE
ADDRESS
BYTE
ADDRESS
BUS ACTIVITY:
MASTER
SLAVE
Figure 12. Sequential Read Sequence
A
C
K
A
C
K
A
C
K
S
T
O
P
N
O
A
C
K
A
C
K
P
SLAVE
ADDRESS
DATA
BYTE
n
DATA
BYTE
n+1
DATE
BYTA
n+2
DATA
BYTE
n+x
BUS ACTIVITY:
MASTER
SLAVE


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