CDCM61001

www.ti.com

SCAS869C – FEBRUARY 2009 – REVISED FEBRUARY 2010

One Output, Integrated VCO, Low-Jitter Clock Generator

Check for Samples: CDCM61001

1

FEATURES

•

Chip Enable and Device Reset Control Pins

Available

2

•

One Crystal Reference Input Including 24.8832

MHz, 25 MHz, and 26.5625 MHz

•

3.3-V Core and I/O Power Supply

•

Input Frequency Range: 21.875 MHz to

•

Industrial Temperature Range: –40°C to +85°C

28.47 MHz

•

5-mm × 5-mm, 32-pin, QFN (RHB) Package

•

On-Chip VCO Operates in Frequency Range of

•

ESD Protection Exceeds 2 kV (HBM)

1.75 GHz to 2.05 GHz

•

1x Output Available:

APPLICATIONS

•

Low Jitter Clock Driver for High-End Datacom

–

Pin-Selectable Between LVPECL, LVDS, or

Applications Including SONET, Ethernet, Fibre

2-LVCMOS; Operates at 3.3 V

Channel, Serial ATA, and HDTV

•

LVCMOS Bypass Output Available

•

Cost-Effective High-Frequency Crystal

•

Output Frequency Selectable by /1, /2, /3, /4, /6,

Oscillator Replacement

/8 from the Output Divider

•

Supports Common LVPECL/LVDS Output

Frequencies:

DESCRIPTION

–

62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,

The CDCM61001 is a highly versatile, low-jitter

100 MHz, 106.25 MHz, 125 MHz, 150 MHz,

frequency synthesizer that can generate low-jitter

155.52 MHz, 156.25 MHz, 159.375 MHz,

clock

outputs,

selectable

between

low-voltage

187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz,

positive emitter coupled logic (LVPECL), low-voltage

311.04 MHz, 312.5 MHz, 622.08 MHz,

differential

signaling

(LVDS),

or

low-voltage

625 MHz

complementary

metal

oxide

semiconductor

(LVCMOS) outputs, from a low-frequency crystal for a

•

Supports Common LVCMOS Output

variety

of

wireline

and

data

communication

Frequencies:

applications. The CDCM61001 features an onboard

–

62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,

PLL that can be easily configured solely through

100 MHz, 106.25 MHz, 125 MHz, 150 MHz,

control

pins.

The

overall

output

random

jitter

155.52 MHz, 156.25 MHz, 159.375 MHz,

performance is less than 1ps, RMS (from 10 kHz to

187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz

20 MHz), making this device a perfect choice for use

in demanding applications such as SONET, Ethernet,

•

Output Frequency Range: 43.75 MHz to

Fibre Channel, and SAN. The CDCM61001 is

683.264 MHz (See Table 3)

available in a small, 32-pin,

5-mm × 5-mm QFN

•

Internal PLL Loop Bandwidth: 400 kHz

package.

•

High-Performance PLL Core:

–

Phase Noise typically at –146 dBc/Hz at

5-MHz Offset for 625-MHz LVPECL Output

–

Random Jitter typically at 0.509 ps, RMS

(10 kHz to 20 MHz) for 625-MHz LVPECL

Output

•

Output Duty Cycle Corrected to 50% (± 5%)

•

Divider Programming Using Control Pins:

–

Two Pins for Prescaler/Feedback Divider

–

Three Pins for Output Divider

–

Two Pins for Output Select

1

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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

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PRODUCTION DATA information is current as of publication date.

Copyright © 2009–2010, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.