数据搜索系统,热门电子元器件搜索 |
|
ADF7021-VBCPZ-RL 数据表(PDF) 9 Page - Analog Devices |
|
ADF7021-VBCPZ-RL 数据表(HTML) 9 Page - Analog Devices |
9 / 60 page ADF7021-V Rev. 0 | Page 9 of 60 DIGITAL SPECIFICATIONS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments TIMING INFORMATION Chip Enabled to Regulator Ready 50 μs CREG[1:4] = 100 nF Chip Enabled to Tx Mode 32-bit register write time = 50 μs TCXO Reference 1 ms Depends on VCO settling XTAL 2 ms Depends on VCO settling Chip Enabled to Rx Mode 32-bit register write time = 50 μs, IF filter coarse calibration only TCXO Reference 1.2 ms Depends on VCO settling XTAL 2.2 ms Depends on VCO settling Tx-to-Rx Turnaround Time AGC settling + (5 × tBIT) ms Time to synchronized data output; includes AGC settling (three AGC levels) and CDR synchronization; tBIT = data bit period; AFC settling not included LOGIC INPUTS Input High Voltage, VINH 0.7 × VDD V Input Low Voltage, VINL 0.2 × VDD V Input Current, IINH/IINL ±1 μA Input Capacitance, CIN 10 pF Control Clock Input 50 MHz LOGIC OUTPUTS Output High Voltage, VOH VDD2 − 0.4 V IOH = 500 μA Output Low Voltage, VOL 0.4 V IOL = 500 μA CLKOUT Rise/Fall Time 5 ns CLKOUT Load 10 pF |
类似零件编号 - ADF7021-VBCPZ-RL |
|
类似说明 - ADF7021-VBCPZ-RL |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |