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AD80066 数据表(PDF) 7 Page - Analog Devices |
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AD80066 数据表(HTML) 7 Page - Analog Devices |
7 / 20 page AD80066 Rev. A | Page 7 of 20 ANALOG INPUTS CDSCLK1 PIXEL n PIXEL (n + 1) PIXEL (n + 2) CDSCLK2 ADCCLK OUTPUT DATA (D[7:0]) NOTES 1. IN 1-CHANNEL CDS MODE. THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS LOW. LOW BYTE HIGH BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE tAD tC1 tAD tC2ADR tOD tC1C2 PIXEL (n – 4) tC2ADF tADCCLK tADCCLK tC2 PIXEL (n – 4) PIXEL (n – 3) PIXEL (n – 3) PIXEL (n – 2) PIXEL (n – 2) tC2C1 tPRB Figure 6. 1-Channel CDS Mode Timing PIXEL n (A, B, C, D) tAD tC2 tC2ADF tADC2 tC2ADR tADCCLK tADCCLK tOD B(n – 2) C(n – 2) C(n – 2) D(n – 2) D(n – 2) D(n) D(n) A(n) A(n) HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE tPRA PIXEL (n + 1) ANALOG INPUTS CDSCLK2 ADCCLK OUTPUT DATA (D[7:0]) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1) Figure 7. 4-Channel SHA Mode Timing |
类似零件编号 - AD80066 |
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类似说明 - AD80066 |
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