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CDCE62005 数据表(PDF) 10 Page - Texas Instruments |
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CDCE62005 数据表(HTML) 10 Page - Texas Instruments |
10 / 80 page Output Divider0 U0P U0N Output Divider1 U1P U1N Output Divider2 U2P U2N Output Divider3 U3P U3N Output Divider4 U4P U4N PFD / CP /1:/2:HiZ Prescaler Feedback Divider Input Divider Reference Divider AUX OUT F IN EXT_LFP EXT_LFN F R I P O F OUT /1:/2:HiZ = ´ ´ ´ OUT IN F F F R I O = ´ IN COMP F F R I CDCE62005 SCAS862C – NOVEMBER 2008 – REVISED FEBRUARY 2010 www.ti.com COMPUTING THE OUTPUT FREQUENCY Figure 9 presents the block diagram of the CDCE62005 in synthesizer mode highlighting the clock path for a single output. It also identifies the following regions containing dividers comprising the complete clock path • R: Includes the cumulative divider values of all dividers included from the Input Ports to the output of the Smart Multiplexer (see Input Block for more details) • O: The output divider value (see Output Block for more details) • I: The input divider value (see Synthesizer Block for more details) • P: The Prescaler divider value (see Synthesizer Block of more details) • F: The cumulative divider value of all dividers falling within the feedback divider (see Synthesizer Block for more details) Figure 9. CDCE62005 Clock Path – Synthesizer Mode With respect to Figure 9, any output frequency generated by the CDCE62005 relates to the input frequency connected to the Synthesizer Block by Equation 1. (1) Equation 1 holds true when subject to the following constraints: 1.750 Ghz < O x P x FOUT< 2.356 GHz (2) And the comparison frequency FCOMP, 40 kHz ≤ FCOMP < 40 MHz Where: Note: This device cannot output the frequencies between 780 MHz to 880 MHz (3) 10 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s) :CDCE62005 |
类似零件编号 - CDCE62005_10 |
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类似说明 - CDCE62005_10 |
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