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74AVCH4T245RSVRG4 数据表(PDF) 2 Page - Texas Instruments |
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74AVCH4T245RSVRG4 数据表(HTML) 2 Page - Texas Instruments |
2 / 22 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) DIR OE A1 B1 A2 B2 SN74AVCH4T245 4-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES577D – JUNE 2004 – REVISED JUNE 2007 Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE(1)(2) ORDERABLE PART NUMBER TOP-SIDE MARKING QFN – RGY Tape and reel SN74AVCH4T245RGYR WS245 QFN – RSV Tape and reel SN74AVCH4T245RSVR ZWV Tube SN74AVCH4T245D SOIC – D AVCH4T245 –40 °C to 85°C Tape and reel SN74AVCH4T245DR Tube SN74AVCH4T245PW TSSOP – PW WS245 Tape and reel SN74AVCH4T245PWR TVSOP – DGV Tape and reel SN74AVCH4T245DGVR WS245 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. FUNCTION TABLE(1) (EACH 2-BIT SECTION) CONTROL INPUTS OUTPUT CIRCUITS OPERATION OE DIR A PORT B PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B bus H X Hi-Z Hi-Z Isolation (1) Input circuits of the data I/Os are always active. LOGIC DIAGRAM (POSITIVE LOGIC) FOR 1/2 OF AVCH4T245 2 Submit Documentation Feedback |
类似零件编号 - 74AVCH4T245RSVRG4 |
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类似说明 - 74AVCH4T245RSVRG4 |
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