数据搜索系统,热门电子元器件搜索 |
|
CS4226-DQ 数据表(PDF) 11 Page - Cirrus Logic |
|
CS4226-DQ 数据表(HTML) 11 Page - Cirrus Logic |
11 / 37 page CS4226 DS188F4 11 2 FUNCTIONAL DESCRIPTION 2.1 Overview The CS4226 has 2 channels of 20-bit analog- to-digital conversion and 6 channels of 20-bit digital-to-analog conversion. A mono 20-bit ADC is also provided. All ADCs and DACs are delta-sigma converters. The stereo ADC in- puts have adjustable input gain, while the DAC outputs have adjustable output attenuation. The device also contains an S/PDIF receiver capable of receiving compressed AC-3/MPEG or uncompressed digital audio data. Digital audio data for the DACs and from the ADCs is communicated over separate serial ports. This allows concurrent writing to and reading from the device. The CS4226 func- tions are controlled via a serial microcontroller interface. Figure 1 shows the recommended connection diagram for the CS4226. 2.2 Analog Inputs 2.2.1 Line Level Inputs AIN1R, AIN1L, AIN2R, AIN2L, AIN3R, AIN3L and AINAUX are the line level input pins (See Figure 1). These pins are internally biased to the CMOUT voltage. A 10 µF DC blocking ca- pacitor placed in series with the input pins al- lows signals centered around 0V to be input to the CS4226. Figure 2 shows an optional dual op amp buffer which combines level shifting with a gain of 0.5 to attenuate the standard line level of 2 Vrms to 1 Vrms. The CMOUT refer- ence level is used to bias the op-amps to ap- proximately one half the supply voltage. With this input circuit, the 10 µF DC blocking caps in Figure 1 may be omitted. Any remaining DC offset will be removed by the internal high- pass filters. Selection of stereo the input pair (AIN1L/R, AIN2L/R or AIN3L/R) for the 20-bit ADC's is accomplished by setting the AIS1/0 bits (ADC analog input mux control), which are accessi- ble in the ADC Control Byte. On-chip anti- aliasing filters follow the input mux providing anti-aliasing for all input channels. The analog inputs may also be configured as differential inputs. This is enabled by setting bits AIS1/0=3. In the differential configuration, the left channel inputs reside on pins 10 and 11, and the right channel inputs reside on pins 12 and 13 as described in Table 2 below. In differential mode, the full scale input level is 2Vrms. Single-ended Pin # Differential Inputs AIN3L Pin 10 AINL+ AIN3R Pin 9 unused AIN2L Pin 11 AINL- AIN2R Pin 12 AINR- AIN1L Pin 14 unused AIN1R Pin 13 AINR+ Table 2. Single-ended vs. Differential Input Pin Assignments + - 100 pF 10 k 20 k + - 10 k 100 pF 5 k 20 k Line In Right Line In Left CMOUT AINxR AINxL 0.47 µ F 3.3 µF 3.3 µF Example Op-Amps are MC34074 or MC33078 Figure 2. Optional Line Input Buffer |
类似零件编号 - CS4226-DQ |
|
类似说明 - CS4226-DQ |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |