74AUP1T58_2

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 02 — 29 September 2009

3 of 17

NXP Semiconductors

74AUP1T58

Low-power configurable gate with voltage-level translator

6.

Pinning information

6.1 Pinning

6.2 Pin description

7.

Functional description

[1]

H = HIGH voltage level;

L = LOW voltage level.

Fig 2.

Pin configuration SOT363

(SC-88)

Fig 3.

Pin configuration SOT886

(XSON6)

Fig 4.

Pin configuration SOT891

(XSON6)

74AUP1T58

BC

GND

AY

001aah836

1

2

3

6

5

4

74AUP1T58

GND

001aah837

B

A

C

Y

Transparent top view

2

3

1

5

4

6

74AUP1T58

GND

001aah838

B

A

C

Y

Transparent top view

2

3

1

5

4

6

Table 3.

Pin description

Symbol

Pin

Description

B

1

data input

GND

2

ground (0 V)

A

3

data input

Y

4

data output

5

supply voltage

C

6

data input

Table 4.

Function table[1]

Input

Output

C

B

A

Y

LLLL

LLH

H

LH

LL

L

HHH

H

LLH

HL

HH

HHL

L

HHHL