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74AUP1G97GF 数据表(PDF) 1 Page - NXP Semiconductors

部件名 74AUP1G97GF
功能描述  Low-power configurable multiple function gate
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

74AUP1G97GF 数据表(HTML) 1 Page - NXP Semiconductors

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1.
General description
The 74AUP1G97 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR,
NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G97 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT− is defined as the input
hysteresis voltage VH.
2.
Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I ESD protection:
N HBM JESD22-A114E exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °Cto+85 °C and −40 °C to +125 °C
74AUP1G97
Low-power configurable multiple function gate
Rev. 04 — 23 June 2009
Product data sheet


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