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74AHC1G79 数据表(PDF) 6 Page - NXP Semiconductors |
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74AHC1G79 数据表(HTML) 6 Page - NXP Semiconductors |
6 / 12 page 74AHC_AHCT1G79_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 2 July 2007 6 of 12 NXP Semiconductors 74AHC1G79; 74AHCT1G79 Single D-type flip-flop; positive-edge trigger 11. Dynamic characteristics [1] tpd is the same as tPLH and tPHL. [2] Typical values are measured at VCC = 3.3 V. [3] Typical values are measured at VCC = 5.0 V. [4] CPD is used to determine the dynamic power dissipation PD (µW). PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. Table 8. Dynamic characteristics GND = 0 V; tr = tf = ≤ 3.0 ns. For test circuit see Figure 6. For waveforms see Figure 5. Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max For type 74AHC1G79 tpd propagation delay CP to Q [1] VCC = 3.0 V to 3.6 V [2] CL = 15 pF - 4.9 8.4 1.0 9.8 1.0 11.5 ns CL = 50 pF - 6.9 12.0 1.0 14.0 1.0 15.5 ns VCC = 4.5 V to 5.5 V [3] CL = 15 pF - 3.5 5.6 1.0 7.0 1.0 8.0 ns CL = 50 pF - 5.1 8.0 1.0 10.0 1.0 11.0 ns tsu set-up time D to CP 3.0 1.0 - 3.0 - 4.0 - ns th hold time D to CP +2.0 −1.0 - 2.0 - 3.0 - ns tW pulse width clock HIGH or LOW 3.0 - - 3.0 - 4.0 - ns fmax maximum frequency 90 - - 90 - 70 - MHz CPD power dissipation capacitance per buffer; CL =50pF;f=1 MHz; VI = GND to VCC [4] -15- - - - - pF For type 74AHCT1G79 tpd propagation delay CP to Q [1] VCC = 4.5 V to 5.5 V [3] CL = 15 pF - 3.5 5.0 1.0 6.0 1.0 8.0 ns CL = 50 pF - 5.0 8.0 1.0 10.0 1.0 11.0 ns tsu set-up time D to CP 3.0 1.0 - 3.0 - 4.0 - ns th hold time D to CP +2.0 −1.0 - 2.0 - 3.0 - ns tW pulse width clock HIGH or LOW 3.0 - - 3.0 - 4.0 - ns fmax maximum frequency 90 - - 90 - 70 - MHz CPD power dissipation capacitance per buffer; CL =50pF;f=1 MHz; VI = GND to VCC [4] -16- - - - - pF |
类似零件编号 - 74AHC1G79 |
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类似说明 - 74AHC1G79 |
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