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74ABT841PW 数据表(PDF) 8 Page - NXP Semiconductors |
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74ABT841PW 数据表(HTML) 8 Page - NXP Semiconductors |
8 / 15 page 74ABT841_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 25 March 2010 8 of 15 NXP Semiconductors 74ABT841 10-bit bus interface latch; 3-state VM = 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 8. Data set-up and hold times 001aae918 VM Dn LE GND VM VM VM VM VM tsu(H) th(H) tsu(L) th(L) GND VI VI a. Input pulse definition b. Test circuit Test data and VEXT levels are given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 9. Test circuit for measuring switching times 001aai298 VM VM tW tW 10 % 90 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % 90 % 10 % 10 % tf tr tr tf VEXT VCC VI VO mna616 DUT CL RT RL RL G Table 8. Test data Input Load VEXT VI fI tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V |
类似零件编号 - 74ABT841PW |
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类似说明 - 74ABT841PW |
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