1.

General description

The 74ABT646A high-performance BiCMOS device combines low static and dynamic

power dissipation with high speed and high output drive.

The 74ABT646A transceiver/register consists of bus transceiver circuits with 3-state

outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of

data directly from the input bus or the internal registers. Data on the A bus or B bus will be

clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH.

Output Enable (OE) and Direction (DIR) pins are provided to control the transceiver

function. In the transceiver mode, data present at the high-impedance port may be stored

in either the A or B register or both.

The Select (SAB, SBA) pins determine whether data is stored or transferred through the

device in real-time. The DIR pin determines which bus receives data when OE is active

(LOW). In isolation mode (OE = HIGH), data from bus A may be stored in the B register

and/or data from bus B may be stored in the A register. When an output function is

disabled, the input function is still enabled and may be used to store and transmit data.

Only one of the two buses, A or B, may be driven at a time. The examples in Figure 5

“Real time bus transfer and storage” on page 6 demonstrate the four fundamental bus

management functions that can be performed with the 74ABT646A.

2.

Features and benefits

74ABT646A

Octal bus transceiver/register; 3-state

Rev. 03 — 15 March 2010

Product data sheet