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PIN DESCRIPTION

Pin Name

Pin No

I/O

Description

ADJ1

3

Input/Output

1

Cell balance bypass control for cell 1 (Timer in for calibration)

ADJ2

4

Output

1

Cell balance bypass control for cell 2

ADJ3

5

Output

1

Cell balance bypass control for cell 3

ADJ4

6

Output

1

Cell balance bypass control for cell 4

AGND

21

Input

Analog ground

AVDD

8

Input

Analog positive supply

CHG

22

Output

Charge MOSFET control output. High output to terminate charge

DCHG

7

Output

Discharge MOSFET control output. High output to terminate discharge

DGND

20

Input

Digital ground

DVDD

9

Input

Digital positive supply

ESCL

11

Output

EEPROM I

ESDA

12

Input/Output

EEPROM I

I

25

Input

2

Current sense resistor battery negative terminal

IGND

24

Input

Current sense resistor ground (pack negative) terminal

LED1

19

Output

4

LED display segment (MSB)

LED2

18

Output

4

LED display segment

LED3

17

Output

4

LED display segment

LED4

16

Output

4

LED display segment

LED5

15

Output

4

LED display segment (LSB)

SCL

14

Input/Output

SMbus clock line

SDA

13

Input/Output

SMbus data line

T

26

Input

3

Temperature sense resistor voltage divider circuits terminal

V1

2

Input

3

Divided voltage input from cell 1 (the cell connect to battery negative

terminal)

V2

1

Input

3

Divided voltage input from cell 2

V3

28

Input

3

Divided voltage input from cell 3

V4

27

Input

3

Divided voltage input from cell 4 (highest voltage)

VP

10

Output

EEPROM positive supply

VREF

23

Output

Voltage regulator’s voltage reference output

Note 1: Input/outputs are TTL compatible level.

Note 2: Input voltage range is –160mV to +80mV.

Note 3: Divided voltage input range should be from 0.5V to 3.5V.

Note 4: Open drain output.

SS4002AG

12/16/2005 Rev.3.01