ADRF6603-EVALZ datasheet(5/24 Pages) AD

部件名	ADRF6603-EVALZ

功能描述	2100 MHz to 2600 MHz Rx Mixer with Integrated Fractional-N PLL and VCO

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ADRF6603

Rev. 0 | Page 5 of 24

LOGIC INPUT AND POWER SPECIFICATIONS

VS = 5 V; ambient temperature (TA) = 25°C; fREF = 38.4 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized

using capacitor DAC (0x1) and IP3SET (3.3 V), unless otherwise noted.

Table 4.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

LOGIC INPUTS

CLK, DATA, LE

Input High Voltage, VINH

1.4

3.3

V

Input Low Voltage, VINL

0

0.7

V

Input Current, IINH/IINL

0.1

μA

Input Capacitance, CIN

5

pF

POWER SUPPLIES

VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins

Voltage Range

4.75

5

5.25

V

Supply Current

PLL only

98

mA

External LO mode (internal PLL disabled,

IP3SET pin = 3.3 V)

163

mA

Internal LO mode (internal PLL enabled,

IP3SET pin = 3.3 V)

261

mA

Power-down mode

30

mA

TIMING CHARACTERISTICS

VCC2 = 5 V ± 5%.

Table 5.

Parameter

Limit

Unit

Description

t1

20

ns min

LE setup time

t2

10

ns min

DATA to CLK setup time

t3

10

ns min

DATA to CLK hold time

t4

25

ns min

CLK high duration

t5

25

ns min

CLK low duration

t6

10

ns min

CLK to LE setup time

t7

20

ns min

LE pulse width

Timing Diagram

CLK

DATA

LE

DB23 (MSB)

DB22

DB2

DB1

(CONTROL BIT C2)

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

t1

t2

t3

t7

t6

t4

t5

Figure 2. Timing Diagram

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制造商	部件名	数据表	功能描述
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