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AD5175BRMZ-10-RL7 数据表(PDF) 5 Page - Analog Devices |
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AD5175BRMZ-10-RL7 数据表(HTML) 5 Page - Analog Devices |
5 / 20 page AD5175 Rev. 0 | Page 5 of 20 Limit at TMIN, TMAX Parameter Conditions1 Min Max Unit Description tRDAC_R-PERF 2 μs RDAC register write command execute time (R-Perf mode) tRDAC_NORMAL 600 ns RDAC register write command execute time (normal mode) tMEMORY_READ 6 μs Memory readback execute time tMEMORY_PROGRAM 350 ms Memory program time tRESET 600 μs Reset 50-TP restore time t POWER-UP 6 2 ms Power-on 50-TP restore time 1 Maximum bus capacitance is limited to 400 pF. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode. 4 Refer to tRDAC_R-PERF and tRDAC_NORMAL for RDAC register write operations. 5 Refer to t MEMORY_READ and tMEMORY_PROGRAM for memory commands operations. 6 Maximum time after VDD − VSS is equal to 2.5 V. Shift Register and Timing Diagrams DATA BITS DB9 (MSB) DB0 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 CONTROL BITS C0 C1 C2 D9 D8 C3 0 0 Figure 2. Shift Register Content RESET t7 t6 t2 t4 t11 t12 t6 t5 t10 t1 SCL SDA PS S P t3 t8 t9 t13 Figure 3. 2-Wire I2C Timing Diagram |
类似零件编号 - AD5175BRMZ-10-RL7 |
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类似说明 - AD5175BRMZ-10-RL7 |
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