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TS128MDOM40H-S 数据表(PDF) 11 Page - Transcend Information. Inc.

部件名 TS128MDOM40H-S
功能描述  40-Pin IDE Flash Module (Horizontal)
Download  39 Pages
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制造商  TRANSCEND [Transcend Information. Inc.]
网页  http://www.transcendusa.com
标志 TRANSCEND - Transcend Information. Inc.

TS128MDOM40H-S 数据表(HTML) 11 Page - Transcend Information. Inc.

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nd
d
d 4
4
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0
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n
n IIID
D
DE
E
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T
T
TS
S
S1
1
12
2
28
8
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M
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8
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Transcend Information Inc.
Ver 1.3
11
True IDE Multiword DMA Mode Read/Write Timing Specification
Item
Mode 0
(ns)
Mode 1
(ns)
Mode 2
(ns)
Mode 3
(ns)
Mode 4
(ns)
t0
Cycle time (min)
1
480
150
120
100
80
tD
-IORD / -IOWR asserted width(min)
1
215
80
70
65
55
tE
-IORD data access (max)
150
60
50
50
45
tF
-IORD data hold (min)
5
5
5
5
5
tG -IORD/-IOWR data setup (min)
100
30
20
15
10
tH -IOWR data hold (min)
20
15
10
5
5
tI
DMACK to –IORD/-IOWR setup (min)
0
0
0
0
0
tJ
-IORD / -IOWR to -DMACK hold (min)
20
5
5
5
5
tKR -IORD negated width (min) 1
50
50
25
25
20
tKW -IOWR negated width (min) 1
215
50
25
25
20
tLR -IORD to DMARQ delay (max)
120
40
35
35
35
tLW -IOWR to DMARQ delay (max)
40
40
35
35
35
tM CS(1:0) valid to –IORD / -IOWR
50
30
25
10
5
tN CS(1:0) hold
15
10
10
10
10
tZ
-DMACK
20
25
25
25
25
Notes:
(1) t0 is the minimum total cycle time and tD is the minimum command active time, while tKR and tKW are the
minimum command recovery time or command inactive time for input and output cycles respectively. The
actual cycle time equals the sum of the actual command active time and the actual command inactive time.
The three timing requirements of t0, tD, tKR, and tKW shall be met. The minimum total cycle time requirement
is greater than the sum of tD and tKR or tKW.for input and output cycles respectively. This means a host
implementation can lengthen either or both of tD and either of tKR, and tKW as needed to ensure that t0 is
equal to or greater than the value reported in the device’s identify device data.


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