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DM9000A 数据表(PDF) 2 Page - Davicom Semiconductor, Inc.

部件名 DM9000A
功能描述  Ethernet Controller with General Processor Interface
Download  60 Pages
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制造商  DAVICOM [Davicom Semiconductor, Inc.]
网页  http://www.davicom.com.tw
标志 DAVICOM - Davicom Semiconductor, Inc.

DM9000A 数据表(HTML) 2 Page - Davicom Semiconductor, Inc.

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DM9000A
Ethernet Controller with General Processor Interface
Final
2
Version: DM9000A-17-DS-F01
May 10, 2006
Content
1. General Description............................................................................................................................................................ 6
2. Block Diagram .................................................................................................................................................................... 6
3. Features ............................................................................................................................................................................... 7
4. Pin Configuration ............................................................................................................................................................... 8
4.1 (16-bit mode) ................................................................................................................................................................. 8
4.2 (8-bit mode) ................................................................................................................................................................... 9
5. Pin Description.................................................................................................................................................................. 10
5.1 Processor Interface ...................................................................................................................................................... 10
5.1.1 8-bit mode pins.......................................................................................................................................................... 10
5.2 EEPROM Interface .......................................................................................................................................................11
5.3 Clock Interface..............................................................................................................................................................11
5.4 LED Interface ...............................................................................................................................................................11
5.5 10/100 PHY/Fiber.........................................................................................................................................................11
5.6 Miscellaneous .............................................................................................................................................................. 12
5.7 Power Pins................................................................................................................................................................... 12
5.8 strap pins table ............................................................................................................................................................ 12
6. Vendor Control and Status Register Set ......................................................................................................................... 13
6.1 Network Control Register (00H).................................................................................................................................. 14
6.2 Network Status Register (01H) .................................................................................................................................... 15
6.3 TX Control Register (02H)........................................................................................................................................... 15
6.4 TX Status Register I ( 03H ) for packet index I ............................................................................................................ 15
6.5 TX Status Register II ( 04H ) for packet index I I......................................................................................................... 16
6.6 RX Control Register ( 05H ) ........................................................................................................................................ 16
6.7 RX Status Register ( 06H ) ........................................................................................................................................... 16
6.8 Receive Overflow Counter Register ( 07H ) ................................................................................................................ 17
6.9 Back Pressure Threshold Register (08H) ..................................................................................................................... 17
6.10 Flow Control Threshold Register ( 09H ) .................................................................................................................. 17
6.11 RX/TX Flow Control Register ( 0AH ) ....................................................................................................................... 19
6.12 EEPROM & PHY Control Register ( 0BH )............................................................................................................... 19
6.13 EEPROM & PHY Address Register ( 0CH ) .............................................................................................................. 19
6.14 EEPROM & PHY Data Register (EE_PHY_L0DH
EE_PHY_H0EH).......................................................... 19


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