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ADE7878 数据表(PDF) 10 Page - Analog Devices |
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ADE7878 数据表(HTML) 10 Page - Analog Devices |
10 / 92 page ADE7878 Rev. 0 | Page 10 of 92 Table 4. HSDC Interface Timing Parameter Parameter Symbol Min Max Unit HSA to SCLK Edge tSS 0 ns HSCLK Period 125 ns HSCLK Low Pulse Width tSL 50 ns HSCLK High Pulse Width tSH 50 ns Data Output Valid After HSCLK Edge tDAV 40 ns Data Output Fall Time tDF 20 ns Data Output Rise Time tDR 20 ns HSCLK Rise Time tSR 10 ns HSCLK Fall Time tSF 10 ns HSD Disable After HSA Rising Edge tDIS 5 ns HSA High After HSCLK Edge tSFS 0 ns MSB LSB INTERMEDIATE BITS tSFS tDIS tSS tSL tDF tSH tDAV tSR tSF tDR HSD HSCLK HSA Figure 4. HSDC Interface Timing 2mA IOL 800µA IOH 1.6V TO OUTPUT PIN CL 50pF Figure 5. Load Circuit for Timing Specifications |
类似零件编号 - ADE7878 |
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类似说明 - ADE7878 |
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