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AD5542ABRUZ 数据表(PDF) 7 Page - Analog Devices

部件名 AD5542ABRUZ
功能描述  2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-/12-Bit nanoDACs in LFCSP
Download  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5542ABRUZ 数据表(HTML) 7 Page - Analog Devices

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Preliminary Technical Data
AD5541A/AD5542A/AD5512AA
Rev. P
rA | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC = NO CO NNE CT
TO P V IE W
3
SCLK
4
DIN
1
REF
2
CS
6VOUT
5CLR
8GND
7VDD
AD5541A-1
(No t to S cale)
Figure 6. AD5541A-1 8-Lead LFCSP Pin Configuration
VOUT 1
A GN D 2
REF 3
CS 4
V DD
8
DG ND
7
DIN
6
SCLK
5
AD5541A
TO P V IE W
(N o t to S cale)
Figure 7. AD5541A 8-Lead SOIC Pin Configuration
NC = NO CO N NE C T
1
VDD
2
VOUT
3
AGND
4
REF
5
CS
10 VLOGIC
9DGND
8LDAC
7DIN
6SCLK
TO P V IE W
AD5541A
(No t to S cale)
Figure 8. AD5541A 10-Lead LFCSP Pin Configuration
NC = NO CONNECT
VDD
1
VOUT
2
AGND
3
REF
4
CS
5
VLOGIC
10
DGND
9
LDAC
8
DIN
7
SCLK
6
AD5541A
TOP VIEW
(Not to Scale)
Figure 9. AD5541A 10-Lead MSOP Pin Configuration
Table 4. AD5541A Pin Function Descriptions
Pin No.
8-Lead
LFCSP
8-Lead
SOIC
10-Lead
LFCSP
10-Lead
MSOP
Mnemonic
Description
6
1
2
2
VOUT
Analog Output Voltage from the DAC.
2
3
3
AGND
Ground Reference Point for Analog Circuitry.
1
3
4
4
REF
Voltage Reference Input for the DAC. Connect to an external 2.5 V reference.
Reference can range from 2 V to VDD.
2
4
5
5
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
3
5
6
6
SCLK
Clock Input. Data is clocked into the input register on the rising edge of SCLK.
Duty cycle must be between 40% and 60%.
4
6
7
7
DIN
Serial Data Input. This device accepts 16-bit words. Data is clocked into the
input register on the rising edge of SCLK.
7
9
9
DGND
Digital Ground. Ground reference for digital circuitry.
7
8
1
1
VDD
Analog Supply Voltage, 5 V ± 10%.
5
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is
low, all LDAC pulses are ignored. When CLR is activated, the input register and
the DAC register are cleared to the model selectable midscale or zeroscale .
10
10
VLOGIC
Logic Power Supply.
8
8
LDAC
LDAC Input. When this input is taken low, the DAC register is simultaneously
updated with the contents of the input register.


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