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ISL32175EFVZ 数据表(PDF) 10 Page - Intersil Corporation |
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ISL32175EFVZ 数据表(HTML) 10 Page - Intersil Corporation |
10 / 22 page 10 FN7529.0 November 19, 2009 Receiver Input to Output Delay tPLH, tPHL (Figure 1) Full 7 11 16 ns Receiver Skew | tPLH - tPHL | tSKD (Figure 1) Full - 0.4 2 ns Prop Delay Skew Chan-to-Chan tSKC-C (Figure 1), (Note 11) Full - 0.7 4 ns Prop Delay Skew Part-to-Part tSKP-P (Figure 1), (Note 12) Full - 1.2 8 ns Receiver Enable to Output High tZH RL = 1kΩ, CL = 15pF, SW = GND (Figure 2), (Notes 15, 21) Full - 57 75 ns Receiver Enable to Output Low tZL RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2), (Notes 15, 21) Full - 59 75 ns Receiver Disable from Output High tHZ RL = 1kΩ, CL = 15pF, SW = GND (Figure 2) Full - 18 30 ns Receiver Disable from Output Low tLZ RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2) Full - 19 30 ns Receiver Enable from Shutdown to Output High tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 2), (Notes 16, 20) Full - - 850 ns Receiver Enable from Shutdown to Output Low tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 2), (Notes 16, 20) Full - - 850 ns NOTES: 10. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 11. Channel-to-channel skew is the magnitude of the worst case delta between any two propagation delays of any two outputs on the same IC, at the same test conditions. 12. tSKP-P is the magnitude of the difference in propagation delays of the specified terminals of two units tested with identical test conditions (VCC, temperature, etc.). 13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 14. EN = 0 indicates that the output(s) under test are disabled via the appropriate logic pin settings. EN = 1 indicates that the logic pins are set to enable the output(s) under test. 15. For ISL32177E and ISL32277E, keep SHDNEN low to avoid entering SHDN. For ISL32175E and ISL32275E ensure that at least one channel remains enabled to prevent SHDN. 16. For ISL32177E and ISL32277E, keep SHDNEN high to enter SHDN when all drivers are disabled. 17. Logic Pins are the enable variants and SHDNEN. 18. EN low and EN high on the ISL32X73E. SHDNEN, EN, EN1-EN4 all high and EN low on the ISL32X77E. 19. EN12 and EN34 low on ISL32X75E. SHDNEN high, with EN1-EN4 low plus EN and EN high on the ISL32X77E. 20. Shutdown is entered by simultaneously disabling all four outputs for at least 600ns. 21. Does not apply to the ISL32173E nor the ISL32273E; only the EN from SHDN parameters apply to these two parts. Electrical Specifications Test Conditions: VCC = 3.0V to 5.5V; VL = VCC (ISL32177E and ISL32277E only); Typicals are at the worst case of VCC = 3.3V or VCC = 5V, TA = +25°C; Unless Otherwise Specified. Boldface limits apply over the operating temperature range. (Notes 10, 14) (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) MIN (Note 13) TYP MAX (Note 13) UNITS ISL32173E, ISL32175E, ISL32177E, ISL32273E, ISL32275E, ISL32277E |
类似零件编号 - ISL32175EFVZ |
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类似说明 - ISL32175EFVZ |
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