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AD5422BREZ 数据表(PDF) 8 Page - Analog Devices |
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AD5422BREZ 数据表(HTML) 8 Page - Analog Devices |
8 / 40 page AD5412/AD5422 Rev. A | Page 8 of 40 TIMING CHARACTERISTICS AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8V, GND = 0 V, REFIN = +5 V external; DVCC = 2.7 V to 5.5 V. VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description WRITE MODE t1 33 ns min SCLK cycle time t2 13 ns min SCLK low time t3 13 ns min SCLK high time t4 13 ns min LATCH delay time t5 40 ns min LATCH high time t5 5 μs min LATCH high time (after a write to the control register) t6 5 ns min Data setup time t7 5 ns min Data hold time t8 40 ns min LATCH low time t9 20 ns min CLEAR pulse width t10 5 μs max CLEAR activation time READBACK MODE t11 90 ns min SCLK cycle time t12 40 ns min SCLK low time t13 40 ns min SCLK high time t14 13 ns min LATCH delay time t15 40 ns min LATCH high time t16 5 ns min Data setup time t17 5 ns min Data hold time t18 40 ns min LATCH low time t19 35 ns max Serial output delay time (CL SDO4 = 15 pF) t20 35 ns max LATCH rising edge to SDO tristate (CL SDO4 = 15 pF) DAISY-CHAIN MODE t21 90 ns min SCLK cycle time t22 40 ns min SCLK low time t23 40 ns min SCLK high time t24 13 ns min LATCH delay time t25 40 ns min LATCH high time t26 5 ns min Data setup time t27 5 ns min Data hold time t28 40 ns min LATCH low time t29 35 ns max Serial output delay time (CL SDO4 = 15 pF) 1 Guaranteed by characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 CL SDO = capacitive load on SDO output. |
类似零件编号 - AD5422BREZ |
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类似说明 - AD5422BREZ |
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