数据搜索系统,热门电子元器件搜索 |
|
CS5566 数据表(PDF) 8 Page - Cirrus Logic |
|
CS5566 数据表(HTML) 8 Page - Cirrus Logic |
8 / 30 page CS5566 8 DS806PP2 5/4/09 SWITCHING CHARACTERISTICS (CONTINUED) TA =-40 to +85°C; V1+= V2+= +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF. 13. SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down resistors. 14. SCLK = MCLK/2. Parameter Symbol Min Typ Max Unit Serial Port Timing in SSC Mode (SMODE = VL) Data hold time after SCLK rising t7 -10- ns Serial Clock (Out) Pulse Width (low) (Note 13, 14) Pulse Width (high) t8 t9 100 100 - - - - ns ns RDY rising after last SCLK rising t10 -8- MCLKs CS falling to MSB stable t11 -10- ns First SCLK rising after CS falling t12 -8- MCLKs CS hold time (low) after SCLK rising t13 10 - - ns SCLK, SDO tri-state after CS rising t14 -5- ns MCLK RDY SCLK(o) SDO CS t12 t8 t13 t9 t7 t11 MSB MSB–1 LSB LSB+1 t14 t10 Figure 3. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale) |
类似零件编号 - CS5566 |
|
类似说明 - CS5566 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |