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STA2500D 数据表(PDF) 8 Page - STMicroelectronics |
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STA2500D 数据表(HTML) 8 Page - STMicroelectronics |
8 / 57 page Quick reference data STA2500D 8/57 Doc ID 16067 Rev 1 2.3 I/O specifications The I/Os comply with the EIA/JEDEC standard JESD8-B. 2.4 Clock specifications The STA2500D supports, on the BT_REF_CLK_IN pin, the system clock both as a sine wave clock and as a digital clock. For configuration, see Table 13: pin BT_VDD_CLD (E6). Table 4. DC input specification Symbol Parameter Min. Typ. Max. Unit VIL_BT Low level input voltage -0.2 - 0.35 * BT_VIO_x V VIH_BT High level input voltage 0.65 * BT_VIO_x - (BT_VIO_x + 0.2) and ( ≤ 2.85) V Cin_BT Input capacitance(1) 1. Except for the system clock. 1- 2.5 pF Rpu Pull-up equivalent resistance (with Vin = 0 V) 31 47 73 k Ω Rpd Pull-down equiv. resistance (with Vin = BT_VIO_x) 29 50 100 k Ω Vhyst Schmitt trigger hysteresis (at BT_VIO_A = 1.8 V) except for BT_CONFIG1-3, BT_RESETN, BT_WAKEUP 0.4 0.5 0.6 V Vhyst Schmitt trigger hysteresis (at BT_VIO_x = 1.8 V) for BT_CONFIG1-3, BT_RESETN, BT_WAKEUP, BT_LP_CLK 0.223 - 0.314 V Vhyst Schmitt trigger hysteresis (at BT_VIO_B = 1.3 V) 0.2 - 0.3 V Table 5. DC output specification Symbol Parameter Condition Min. Typ. Max. Unit VOL_BT Low level output voltage Id = X (1) mA 1. X is the source/sink current under worst-case conditions according to the drive capabilities (see Section 3) -- 0.15 V VOH_BT High level output voltage Id = X (1) mA BT_VIO_x - 0.25 -- V Table 6. System clock supported frequencies Symbol Parameter Values Unit FIN Clock input frequency list 9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6, 38.4 MHz Table 7. System clock overall specifications Symbol Parameter Min. Typ. Max. Unit FINTOL Tolerance on input frequency -20 - 20 ppm |
类似零件编号 - STA2500D |
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