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TSB41LV06 数据表(PDF) 7 Page - Texas Instruments |
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TSB41LV06 数据表(HTML) 7 Page - Texas Instruments |
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7 / 39 page  TSB41LV06 IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER SLLS289 – JANAURY1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL TYPE I/O DESCRIPTION NAME NO. LPS 24 CMOS 5 V tol I Link power status input. This pin is used to monitor the power status of the LLC, and is connected to either the VDD supplying the link layer controller through a 1k Ω resistor, or to a pulsed output which is active when the LLC is powered. The pulsed output is useful when using an isolation barrier. If this input is low for more than 2.6 µs, the LLC is considered powered-down. If this input is high for more than 20 ns, the LLC is considered powered-up. If the LLC is powered-down, the PHY-LLC interface is disabled, and the TSB41LV06 will perform only the basic repeater functions required for network initialization and operation. Bus holder is built into this terminal. LREQ 3 CMOS 5 V tol I LLC request input. The LLC uses this input to initiate a service request to the TSB41LV06. Bus Holder is built into this terminal. PC0 PC1 PC2 28 29 30 CMOS I Power class programming inputs. On hardware reset, these inputs set the default value of the power–class indicated during self-ID. Programmed is done by tying the pins high or low. Refer to Table 9 for encoding. PD 23 CMOS 5 V tol I Power-down input. A high on this pin turns off all internal circuitry except the cable-active monitor circuits, which control the CNA output. Bus Holder is built into this terminal. PLLGND 94, 95 Supply – PLL circuit ground pins. These pins should be tied together to the low impedance circuit board ground plane. PLLVDD 93 Supply – PLL circuit power pins. A combination of high frequency decoupling capacitors near each pin are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering capacitors are also recommended. These supply pins are separated from DVDD and AVDD internal to the device to provide noise isolation. They should be tied at a low impedance point on the circuit board. RESET 98 CMOS I Logic reset input. Asserting this pin low resets the internal logic. An internal pull–up resistor to VDD is provided so only an external delay capacitor in parallel with a resistor is required for proper power-up operation (see power–up reset in the applications information section). This input is otherwise a standard logic input, and may also be driven by an open-drain type driver. R0 R1 83 84 Bias – Current setting resistor pins. These pins are connected to an external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.30 k Ω ±0.5% is required to meet the IEEE Std 1394-1995 output voltage limits. SE 42 CMOS I Test control input. This input is used in manufacturing test of the TSB41LV06. For normal use this pin should be tied to GND through a 1-k Ω resistor. SM 43 CMOS I Test control input. This input is used in manufacturing test of the TSB41LV06. For normal use this pin should be tied to GND. SYSCLK 5 CMOS O System clock output. Provides a 49.152 MHz clock signal, synchronized with data transfers, to the LLC. TESTM 41 CMOS I Test control input. This input is used in manufacturing test of the TSB41LV06. For normal use this pin should be tied to VDD. TPA0+ TPA1+ TPA2+ TPA3+ TPA4+ TPA5+ 39 55 61 67 73 88 Cable I/O Twisted-pair cable A differential signal pins. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. |
类似零件编号 - TSB41LV06 |
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类似说明 - TSB41LV06 |
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