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TSB41LV01PAP 数据表(PDF) 7 Page - Texas Instruments |
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TSB41LV01PAP 数据表(HTML) 7 Page - Texas Instruments |
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7 / 49 page  TSB41LV01 IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER SLLS365 – AUGUST 1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AGND 32, 33, 39, 48, 49, 50 – Analog circuit ground pins. These pins should be tied together to the low impedance circuit board ground plane. AVDD 30, 31, 42, 51, 52 – Analog circuit power pins. A combination of high frequency decoupling capacitors near each pin is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering capacitors are also recommended. These supply pins are separated from PLLVDD and DVDD internal to the device to provide noise isolation. They should be tied at a low impedance point on the circuit board. C/LKON 19 I/O Bus manager contender programming input and link-on output. On hardware reset, this pin is used to set the default value of the contender status indicated during self-ID. Programming is done by tying the pin through a 10 k Ω resistor to a high (contender) or low (not contender). The resistor allows the link-on output to override the input. However, it is recommended that this pin should be programmed low, and that the contender status be set via the C register bit. If the TSB41LV01 is used with an LLC that has a dedicated pin for monitoring LKON and also setting the contender status, then a 1-k Ω series resistor should be placed on the LKON line between the Phy and LLC to prevent bus contention. Following hardware reset, this pin is the Link-On output, which is used to notify the LLC to power-up and become active. The Link-On output is a square-wave signal with a period of approximately 163 ns (8 SYSCLK cycles) when active. The Link-On output is otherwise driven low, except during Hardware Reset when it is high impedance. The Link-On output is activated if the LLC is inactive (LPS inactive or the LCtrl bit cleared) and when: a) the Phy receives a link-on Phy packet addressed to this node, b) the PEI (port-event interrupt) register bit is 1, or c) any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or STOI (state-timeout interrupt) register bits are 1 and the RPIE (resuming-port interrupt enable) register bit is also 1. Once activated, the Link-On output will continue active until the LLC becomes active (both LPS active and the LCtrl bit set). The Phy also deasserts the Link-On output when a bus-reset occurs unless the Link-On output would otherwise be active because one of the interrupt bits is set (i.e., the Link-On output is active due solely to the reception of a link-on Phy packet). NOTE: If an interrupt condition exists which would otherwise cause the Link-On output to be activated if the LLC were inactive, the Link-On output will be activated when the LLC subsequently becomes inactive. CNA 3 O Cable Not Active output. This pin is asserted high when the port is not receiving incoming bias voltage. CPS 24 I Cable Power Status input. This pin is normally connected to cable power through a 400 k Ω resistor. This circuit drives an internal comparator that is used to detect the presence of cable power. CTL0 CTL1 4 5 I/O Control I/Os. These bidirectional signals control communication between the TSB41LV01 and the LLC. Bus holders are built into these terminals. D0 – D7 6, 7, 8, 9, 10, 11, 12, 13 I/O Data I/Os. These are bidirectional data signals between the TSB41LV01 and the LLC. Bus holders are built into these terminals. DGND 17, 18, 63, 64 – Digital circuit ground pins. These pins should be tied together to the low impedance circuit board ground plane. DVDD 25, 26, 61, 62 – Digital circuit power pins. A combination of high frequency decoupling capacitors near each pin are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering capacitors are also recommended. These supply pins are separated from PLLVDD and AVDD internal to the device to provide noise isolation. They should be tied at a low impedance point on the circuit board. FILTER0 FILTER1 54 55 I/O PLL filter pins. These pins are connected to an external capacitance to form a lag-lead filter required for stable operation of the internal frequency multiplier PLL running off of the crystal oscillator. A 0.1 µF ±10% capacitor is the only external component required to complete this filter. |
类似零件编号 - TSB41LV01PAP |
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类似说明 - TSB41LV01PAP |
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