TSB12LV22PZP datasheet(10/45 Pages) TI

部件名	TSB12LV22PZP

功能描述	OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER

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制造商	TI [Texas Instruments]

网页	http://www.ti.com

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10 / 45 page

TSB12LV22

OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER

SLLS290 – JULY 1998

10

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 6. Bit Descriptions – Class Code and Revision ID Register

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:24

BASECLASS

r

Base Class. This field returns 0Ch when read, which broadly classifies the function as a serial bus

controller.

23:16

SUBCLASS

r

Sub Class. This field returns 00h when read, which specifically classifies the function as controlling a

IEEE1394 serial bus.

15:8

PGMIF

r

Programming Interface. This field returns 10h when read, which indicates that the programming

model is compliant with the 1394 OHCI specification.

7:0

CHIPREV

r

Silicon Revision. This field returns 01h when read, indicating the silicon revision of the OHCI-Lynx.

latency timer and class cache line size register

This register is programmed by host BIOS to indicate system cache line size and the latency timer associated

with the OHCI-Lynx.

PCI register 0Ch

BIT NUMBER

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reset State

0

Table 7. Bit Descriptions – Latency Timer and Class Cache Line Size Register

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8

LATENCY_TIMER

rw

PCI Latency Timer. The value in this register specifies the latency timer for the OHCI-Lynx, in

units of PCI clock cycles. When the OHCI-Lynx is a PCI bus initiator and asserts FRAME, the

latency timer will begin counting from zero. If the latency timer expires before the OHCI-Lynx

transaction has terminated, then the OHCI-Lynx will terminate the transaction when its GNT is

deasserted.

7:0

CACHELINE_SZ

rw

Cache Line Size. This value is used by the OHCI-Lynx during Memory Write and Invalidate,

Memory Read Line, and Memory Read Multiple transactions.

header type and bist register

This register indicates the OHCI-Lynx PCI header type, and indicates no built-in self test.

PCI register 0Eh

BIT NUMBER

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reset State

0

Table 8. Bit Descriptions – Header Type and Bist Register

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8

BIST

r

Built-in Self Test. The OHCI-Lynx does not include a built-in self test, and this field returns zero

when read.

7:0

HEADER_TYPE

r

PCI Header Type. The OHCI-Lynx includes the standard PCI header, and this is communicated

by returning zero when this field is read.

类似零件编号 - TSB12LV22PZP

制造商	部件名	数据表	功能描述
Texas Instruments	TSB12LV22PZ	586Kb / 45P	[Old version datasheet] OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER

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