TPIC1501 datasheet(1/17 Pages) TI

部件名	TPIC1501

功能描述	QUAD AND HEX POWER DMOS ARRAY

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制造商	TI [Texas Instruments]

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TPIC1501A

QUAD AND HEX POWER DMOS ARRAY

SLIS046A – MAY 1995 – REVISED JUNE 1996

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Low rDS(on):

0.1

Ω Typ (Full H-Bridge)

0.4

Ω Typ (Triple Half H-Bridge)

D Pulsed Current:

12 A Per Channel (Full H-Bridge)

6 A Per Channel (Triple Half H-Bridge)

D Matched Sense Transistor for Class A-B

Linear Operation

D Fast Commutation Speed

description

The TPIC1501A is a monolithic power array that

consists of ten electrically isolated N-channel

enhancement-mode power DMOS transistors, four

of which are configured as a full H-bridge and six as

a triple half H-bridge. The lower stage of the full

H-bridge features an integrated sense FET to allow

biasing of the bridge in class A-B operation.

The TPIC1501A is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for

operation over the case temperature range of – 40

°C to 125°C.

schematic

Q4B

GATE1A

17

OUTPUT1

19

GATE1B

21

Q2A

8

Q2B

6

4

D1

D2

GATE3A

22

OUTPUT3

1

GATE3B

3

D3

GATE4A

Q4A

18

OUTPUT4

11

GATE4B

7

GATE2A

OUTPUT2

GATE2B

Q3B

Q3A

15

10

Q1B

Q1A

Q5B

GATE5A

Q5A

16

OUTPUT5

13

GATE5B

9

14, 24

12

2, 23

GND

SOURCE

VDD1

VDD2

VDD3

Q2C

20

5

GATE2C

SENSE

NOTES: A. Pins 2 and 23 must be externally connected.

B. Pins 14 and 24 must be externally connected.

C. No output may be taken greater than 0.5 V below GND.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

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3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

OUTPUT3

GND

GATE3B

GATE2B

SENSE

OUTPUT2

GATE4B

GATE2A

GATE5B

VDD2

OUTPUT4

SOURCE

VDD3

GND

GATE3A

GATE1B

GATE2C

OUTPUT1

GATE4A

GATE1A

GATE5A

VDD1

VDD3

OUTPUT5

DW PACKAGE

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